| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/XCore/ |
| H A D | XCoreMachineFunctionInfo.cpp | 53 TRI.getSpillAlign(RC), true); in createLRSpillSlot()
67 MFI.CreateStackObject(TRI.getSpillSize(RC), TRI.getSpillAlign(RC), true); in createFPSpillSlot()
80 Align Alignment = TRI.getSpillAlign(RC); in createEHSpillSlot()
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| H A D | XCoreFrameLowering.cpp | 580 Align Alignment = TRI.getSpillAlign(RC); in processFunctionBeforeFrameFinalized()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Mips/ |
| H A D | MipsMachineFunction.cpp | 166 TRI.getSpillAlign(RC), false); in createEhDataRegsFI()
180 TRI.getSpillAlign(RC), false); in createISRRegFI()
206 TRI.getSpillSize(*RC), TRI.getSpillAlign(*RC), false); in getMoveF64ViaSpillFI()
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| H A D | MipsSEFrameLowering.cpp | 898 TRI->getSpillAlign(RC), false); in determineCalleeSaves()
914 TRI->getSpillAlign(RC), false); in determineCalleeSaves()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86LowerTileCopy.cpp | 91 Align Alignment = TRI->getSpillAlign(X86::TILERegClass); in runOnMachineFunction()
95 Alignment = TRI->getSpillAlign(X86::GR64RegClass); in runOnMachineFunction()
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| H A D | X86FastPreTileConfig.cpp | 128 Align Alignment = TRI->getSpillAlign(RC); in getStackSpaceFor()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonVExtract.cpp | 140 Align Alignment = HRI.getSpillAlign(VecRC); in runOnMachineFunction()
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| H A D | HexagonFrameLowering.cpp | 1683 Align Alignment = std::min(TRI->getSpillAlign(*RC), getStackAlign()); in assignCalleeSavedSpillSlots()
1906 Align NeedAlign = HRI.getSpillAlign(Hexagon::HvxVRRegClass); in expandStoreVec2()
1953 Align NeedAlign = HRI.getSpillAlign(Hexagon::HvxVRRegClass); in expandLoadVec2()
1992 Align NeedAlign = HRI.getSpillAlign(Hexagon::HvxVRRegClass); in expandStoreVec()
2020 Align NeedAlign = HRI.getSpillAlign(Hexagon::HvxVRRegClass); in expandLoadVec()
2123 Align A = HRI.getSpillAlign(*RC); in determineCalleeSaves()
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| H A D | HexagonInstrInfo.cpp | 1175 Align NeedAlign = HRI.getSpillAlign(Hexagon::HvxVRRegClass); in expandPostRAPseudo()
1191 Align NeedAlign = HRI.getSpillAlign(Hexagon::HvxVRRegClass); in expandPostRAPseudo()
1213 Align NeedAlign = HRI.getSpillAlign(Hexagon::HvxVRRegClass); in expandPostRAPseudo()
1230 Align NeedAlign = HRI.getSpillAlign(Hexagon::HvxVRRegClass); in expandPostRAPseudo()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | SILowerSGPRSpills.cpp | 238 TRI->getSpillAlign(*RC), true); in spillCalleeSavedRegs()
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| H A D | SIMachineFunctionInfo.cpp | 561 TRI.getSpillAlign(AMDGPU::SGPR_32RegClass), false); in getScavengeFI()
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| H A D | SIFrameLowering.cpp | 82 Align Alignment = TRI->getSpillAlign(RC); in getVGPRSpillLaneOrTempRegister()
1347 TRI->getSpillAlign(*RC)); in processFunctionBeforeFrameFinalized()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | RegisterScavenging.cpp | 231 Align NeedAlign = TRI->getSpillAlign(RC); in spill()
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| H A D | VirtRegMap.cpp | 97 Align Alignment = TRI->getSpillAlign(*RC); in createSpillSlot()
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| H A D | PrologEpilogInserter.cpp | 514 Align Alignment = RegInfo->getSpillAlign(*RC); in assignCalleeSavedSpillSlots()
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| H A D | RegAllocFast.cpp | 449 Align Alignment = TRI->getSpillAlign(RC); in getStackSpaceFor()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/LoongArch/ |
| H A D | LoongArchFrameLowering.cpp | 169 int FI = MFI.CreateStackObject(RI->getSpillSize(RC), RI->getSpillAlign(RC), in processFunctionBeforeFrameFinalized()
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| /freebsd-14.2/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | TargetRegisterInfo.h | 298 Align getSpillAlign(const TargetRegisterClass &RC) const { in getSpillAlign() function
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/ARC/ |
| H A D | ARCFrameLowering.cpp | 443 RegInfo->getSpillAlign(*RC), false); in processFunctionBeforeFrameFinalized()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/CSKY/ |
| H A D | CSKYFrameLowering.cpp | 442 Align align = TRI->getSpillAlign(*RC); in determineCalleeSaves()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVFrameLowering.cpp | 1231 RegInfo->getSpillAlign(*RC), false); in processFunctionBeforeFrameFinalized()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/SystemZ/ |
| H A D | SystemZFrameLowering.cpp | 1042 Align Alignment = TRI->getSpillAlign(*RC); in assignCalleeSavedSpillSlots()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64FrameLowering.cpp | 3405 Align Alignment = TRI->getSpillAlign(RC); in determineCalleeSaves()
3471 Align Alignment(RegInfo->getSpillAlign(*RC)); in assignCalleeSavedSpillSlots()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCFrameLowering.cpp | 2302 Align Alignment = TRI.getSpillAlign(RC); in addScavengingSpillSlot()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMFrameLowering.cpp | 2771 Align Alignment = TRI->getSpillAlign(RC); in determineCalleeSaves()
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