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Searched refs:getSExtValue (Results 1 – 25 of 245) sorted by relevance

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/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonDepOperands.td18 defm s6_0ImmPred : ImmOpPred<[{ return isShiftedInt<6, 0>(N->getSExtValue());}]>;
21 defm s32_0ImmPred : ImmOpPred<[{ return isShiftedInt<32, 0>(N->getSExtValue());}]>;
24 defm u10_0ImmPred : ImmOpPred<[{ return isShiftedUInt<10, 0>(N->getSExtValue());}]>;
27 defm u32_0ImmPred : ImmOpPred<[{ return isShiftedUInt<32, 0>(N->getSExtValue());}]>;
30 defm m32_0ImmPred : ImmOpPred<[{ return isShiftedInt<32, 0>(N->getSExtValue());}]>;
33 defm b13_2ImmPred : ImmOpPred<[{ return isShiftedInt<13, 2>(N->getSExtValue());}]>;
54 defm s3_0ImmPred : ImmOpPred<[{ return isShiftedInt<3, 0>(N->getSExtValue());}]>;
57 defm s4_0ImmPred : ImmOpPred<[{ return isShiftedInt<4, 0>(N->getSExtValue());}]>;
60 defm s4_1ImmPred : ImmOpPred<[{ return isShiftedInt<4, 1>(N->getSExtValue());}]>;
63 defm s4_2ImmPred : ImmOpPred<[{ return isShiftedInt<4, 2>(N->getSExtValue());}]>;
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H A DHexagonOperands.td13 def s8_0Imm64Pred : PatLeaf<(i64 imm), [{ return isInt<8>(N->getSExtValue()); }]>;
19 int64_t v = (int64_t)N->getSExtValue();
23 int64_t v = (int64_t)N->getSExtValue();
H A DHexagonOptimizeSZextends.cpp109 if (!(C && C->getSExtValue() == 16)) in runOnFunction()
120 if (!(C && C->getSExtValue() == 16)) in runOnFunction()
H A DHexagonIntrinsics.td112 int64_t V = N->getSExtValue();
150 int32_t V = N->getSExtValue();
155 int32_t V = N->getSExtValue();
245 int64_t v = (int64_t)(64 - N->getSExtValue());
250 int64_t v = (int64_t)(128 - N->getSExtValue());
255 int32_t Imm = N->getSExtValue();
260 int32_t Imm = N->getSExtValue();
H A DHexagonISelDAGToDAG.cpp75 int32_t Inc = cast<ConstantSDNode>(Offset.getNode())->getSExtValue(); in INITIALIZE_PASS()
584 int32_t ShlConst = cast<ConstantSDNode>(Shl_1)->getSExtValue(); in SelectSHL()
591 int32_t ValConst = C->getSExtValue() << ShlConst; in SelectSHL()
607 if (C1->getSExtValue() != 0 || Sub_1.getOpcode() != ISD::SHL) in SelectSHL()
612 int32_t ValConst = 1 << (ShlConst + C2->getSExtValue()); in SelectSHL()
746 unsigned Opc = (cast<ConstantSDNode>(N)->getSExtValue() != 0) in SelectConstant()
844 int Mask = -cast<ConstantSDNode>(A.getNode())->getSExtValue(); in SelectVAlignAddr()
1652 int64_t V = CN->getSExtValue(); in isPositiveHalfWord()
1762 cast<ConstantSDNode>(L.Value)->getSExtValue() == 1) in push()
1765 cast<ConstantSDNode>(L.Value)->getSExtValue() == 0) in push()
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/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Lanai/
H A DLanaiISelDAGToDAG.cpp97 return isInt<21>(CN.getSExtValue()) && ((CN.getSExtValue() & 0x3) == 0); in canBeRepresentedAsSls()
113 int32_t Imm = CN->getSExtValue(); in INITIALIZE_PASS()
134 if (isInt<16>(CN->getSExtValue())) { in selectAddrRiSpls()
135 int16_t Imm = CN->getSExtValue(); in selectAddrRiSpls()
147 if (isInt<10>(CN->getSExtValue())) { in selectAddrRiSpls()
148 int16_t Imm = CN->getSExtValue(); in selectAddrRiSpls()
178 if ((RiMode && isInt<16>(CN->getSExtValue())) || in selectAddrRiSpls()
179 (!RiMode && isInt<10>(CN->getSExtValue()))) { in selectAddrRiSpls()
190 Offset = CurDAG->getTargetConstant(CN->getSExtValue(), DL, MVT::i32); in selectAddrRiSpls()
264 if (isInt<16>(CN->getSExtValue())) in selectAddrRr()
H A DLanaiTargetTransformInfo.h67 if (isInt<16>(Imm.getSExtValue())) in getIntImmCost()
71 if (isInt<32>(Imm.getSExtValue())) { in getIntImmCost()
72 if ((Imm.getSExtValue() & 0xFFFF) == 0) in getIntImmCost()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/ARC/
H A DARCISelDAGToDAG.cpp107 int32_t RHSC = RHS->getSExtValue(); in SelectAddrModeS9()
136 int32_t RHSC = RHS->getSExtValue(); in SelectAddrModeFar()
159 (CN->getSExtValue() % 4 == 0 && CN->getSExtValue() >= 0)) { in SelectFrameADDR_ri()
163 CurDAG->getTargetConstant(CN->getSExtValue(), SDLoc(Addr), MVT::i32); in SelectFrameADDR_ri()
/freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DSelectionDAGAddressAnalysis.cpp215 Offset += C->getSExtValue(); in matchLSNode()
220 Offset -= C->getSExtValue(); in matchLSNode()
232 Offset += C->getSExtValue(); in matchLSNode()
239 Offset += C->getSExtValue(); in matchLSNode()
250 auto Off = C->getSExtValue(); in matchLSNode()
293 Offset += cast<ConstantSDNode>(Index->getOperand(1))->getSExtValue(); in matchLSNode()
/freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/
H A DGIMatchTableExecutor.cpp35 return VRegVal->Value.getSExtValue() == Value; in isOperandImmEqual()
39 return VRegVal->getSExtValue() == Value; in isOperandImmEqual()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/
H A DAArch64GlobalISelUtils.cpp30 return RegOrConstant(ValAndVReg->Value.getSExtValue()); in getAArch64VectorSplat()
73 if (!Zero || Zero->Value.getSExtValue() != 0) in tryEmitBZero()
84 if (Size->Value.getSExtValue() <= 256) in tryEmitBZero()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/LoongArch/
H A DLoongArchISelDAGToDAG.cpp48 int64_t Imm = cast<ConstantSDNode>(Node)->getSExtValue(); in INITIALIZE_PASS()
161 if (isIntN(12, CN->getSExtValue())) { in SelectInlineAsmMemoryOperand()
175 if (isIntN(16, CN->getSExtValue()) && in SelectInlineAsmMemoryOperand()
211 int64_t CVal = cast<ConstantSDNode>(Addr)->getSExtValue(); in SelectAddrConstant()
358 SplatVal = CurDAG->getTargetConstant(ImmValue.getSExtValue(), SDLoc(N), in selectVSplatImm()
H A DLoongArchISelLowering.cpp962 if ((IsSigned && !isInt<N>(CImm->getSExtValue())) || in checkIntrinsicImmArg()
2163 if (CN->getSExtValue() >= -2048 && CN->getSExtValue() < 0) in performANDCombine()
2252 isShiftedMask_64(~CN0->getSExtValue(), MaskIdx0, MaskLen0) && in performORCombine()
2274 isShiftedMask_64(~CN0->getSExtValue(), MaskIdx0, MaskLen0) && in performORCombine()
2297 isShiftedMask_64(~CN0->getSExtValue(), MaskIdx0, MaskLen0) && in performORCombine()
2300 (CN1->getSExtValue() & CN0->getSExtValue()) == 0) { in performORCombine()
2341 (CN1->getSExtValue() & CN0->getSExtValue()) == 0) { in performORCombine()
2468 if ((IsSigned && !isInt<N>(CImm->getSExtValue())) || in legalizeIntrinsicImmArg()
2485 if ((IsSigned && !isInt<N>(CImm->getSExtValue())) || in lowerVectorSplatImm()
4760 uint64_t CVal = C->getSExtValue(); in LowerAsmOperandForConstraint()
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/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/VE/
H A DVEISelDAGToDAG.cpp151 if (isInt<32>(CN->getSExtValue())) { in selectADDRzii()
182 if (isInt<32>(CN->getSExtValue())) { in selectADDRzi()
234 if (isInt<32>(CN->getSExtValue())) { in matchADDRri()
274 bool BCTrueMask = (BConst->getSExtValue() != 0); in Select()
/freebsd-14.2/contrib/llvm-project/llvm/lib/DebugInfo/PDB/Native/
H A DNativeSymbolEnumerator.cpp84 int64_t N = Record.Value.getSExtValue(); in getValue()
123 return Variant{Record.Value.getSExtValue()}; in getValue()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZTargetTransformInfo.cpp87 if (isInt<32>(Imm.getSExtValue())) in getIntImmCost()
134 if (isInt<16>(Imm.getSExtValue())) in getIntImmCostInst()
141 if (isInt<32>(Imm.getSExtValue())) in getIntImmCostInst()
155 if (isUInt<32>(-Imm.getSExtValue())) in getIntImmCostInst()
162 if (isInt<32>(Imm.getSExtValue())) in getIntImmCostInst()
249 if (isUInt<32>(-Imm.getSExtValue())) in getIntImmCostIntrin()
257 if (isInt<32>(Imm.getSExtValue())) in getIntImmCostIntrin()
262 if ((Idx < 2) || (Imm.getBitWidth() <= 64 && isInt<64>(Imm.getSExtValue()))) in getIntImmCostIntrin()
267 if ((Idx < 4) || (Imm.getBitWidth() <= 64 && isInt<64>(Imm.getSExtValue()))) in getIntImmCostIntrin()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/XCore/
H A DXCoreISelDAGToDAG.cpp107 && (CN->getSExtValue() % 4 == 0 && CN->getSExtValue() >= 0)) { in SelectADDRspii()
110 Offset = CurDAG->getTargetConstant(CN->getSExtValue(), SDLoc(Addr), in SelectADDRspii()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/BPF/
H A DBPFISelDAGToDAG.cpp120 if (isInt<16>(CN->getSExtValue())) { in INITIALIZE_PASS()
127 Offset = CurDAG->getTargetConstant(CN->getSExtValue(), DL, MVT::i64); in INITIALIZE_PASS()
147 if (isInt<16>(CN->getSExtValue())) { in SelectFIAddr()
154 Offset = CurDAG->getTargetConstant(CN->getSExtValue(), DL, MVT::i64); in SelectFIAddr()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/ARM/MCTargetDesc/
H A DARMAddressingModes.h656 int32_t Exp = (Imm.lshr(10).getSExtValue() & 0x1f) - 15; // -14 to 15 in getFP16Imm()
694 int32_t Exp = (Imm.lshr(23).getSExtValue() & 0xff) - 127; // -126 to 127 in getFP32Imm()
722 int64_t Exp = (Imm.lshr(52).getSExtValue() & 0x7ff) - 1023; // -1022 to 1023 in getFP64Imm()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Transforms/Vectorize/
H A DLoadStoreVectorizer.cpp1130 cast<ConstantInt>(OtherInstrB->getOperand(1))->getSExtValue(); in checkIfSafeAddSequence()
1132 IdxDiff.getSExtValue() == CstVal) in checkIfSafeAddSequence()
1140 cast<ConstantInt>(OtherInstrA->getOperand(1))->getSExtValue(); in checkIfSafeAddSequence()
1142 IdxDiff.getSExtValue() == -CstVal) in checkIfSafeAddSequence()
1155 cast<ConstantInt>(OtherInstrA->getOperand(1))->getSExtValue(); in checkIfSafeAddSequence()
1157 cast<ConstantInt>(OtherInstrB->getOperand(1))->getSExtValue(); in checkIfSafeAddSequence()
1159 IdxDiff.getSExtValue() == (CstValB - CstValA)) in checkIfSafeAddSequence()
1231 IdxDiff.sle(cast<ConstantInt>(OpB->getOperand(1))->getSExtValue()) && in getConstantOffsetComplexAddrs()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVISelDAGToDAG.cpp622 int64_t Val = Cst->getSExtValue(); in tryShrinkShlLogicImm()
770 int64_t Offset = C->getSExtValue(); in tryIndexedLoad()
847 int64_t Imm = ConstNode->getSExtValue(); in Select()
1154 bool IsCANDI = isInt<6>(N1C->getSExtValue()); in Select()
1437 int64_t CVal = C->getSExtValue(); in Select()
1496 int64_t CVal = C->getSExtValue(); in Select()
2265 int64_t CVal = cast<ConstantSDNode>(Addr)->getSExtValue(); in selectConstantAddr()
2361 isInt<12>(C1->getSExtValue())) { in SelectAddrRegRegScale()
2651 int64_t CVal = C->getSExtValue(); in selectSETCC()
3060 int64_t Offset = C->getSExtValue(); in selectSimm5Shl2()
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/freebsd-14.2/contrib/llvm-project/clang/lib/AST/Interp/
H A DInterpBuiltin.cpp83 Integral<64, true>::from(Val.getSExtValue())); in pushAPSInt()
87 Integral<32, true>::from(Val.getSExtValue())); in pushAPSInt()
91 Integral<16, true>::from(Val.getSExtValue())); in pushAPSInt()
95 Integral<8, true>::from(Val.getSExtValue())); in pushAPSInt()
580 pushLong(S, Val.getSExtValue()); in interp__builtin_expect()
944 FieldPtr.deref<T>() = T::from(IntValue.getSExtValue())); in SetThreeWayComparisonField()
/freebsd-14.2/contrib/llvm-project/clang/lib/StaticAnalyzer/Checkers/
H A DMmapWriteExecChecker.cpp57 int64_t Prot = ProtLoc->getValue().getSExtValue(); in checkPreCall()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUISelDAGToDAG.cpp1064 if (isDSOffsetLegal(N0, C1->getSExtValue())) { in SelectDS1Addr1Offset()
1073 int64_t ByteOffset = C->getSExtValue(); in SelectDS1Addr1Offset()
1174 if (ImmOp->getSExtValue() < 0 && ImmOp->getSExtValue() > -0x40000000) in isFlatScratchBaseLegal()
1213 (RHSImm->getSExtValue() < 0 && RHSImm->getSExtValue() > -0x40000000))) in isFlatScratchBaseLegalSVImm()
1416 if (C->getSExtValue()) { in SelectMUBUFAddr64()
1455 int64_t Imm = CAddr->getSExtValue(); in SelectMUBUFScratchOffen()
1574 if (!cast<ConstantSDNode>(Offen)->getSExtValue() && in SelectMUBUFOffset()
1575 !cast<ConstantSDNode>(Idxen)->getSExtValue() && in SelectMUBUFOffset()
1576 !cast<ConstantSDNode>(Addr64)->getSExtValue()) { in SelectMUBUFOffset()
3295 unsigned Imm = C->getAPIntValue().getSExtValue(); in SelectWMMAVISrc()
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/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCTargetTransformInfo.cpp180 if (isInt<16>(Imm.getSExtValue())) in getIntImmCost()
183 if (isInt<32>(Imm.getSExtValue())) { in getIntImmCost()
214 if ((Idx == 1) && Imm.getBitWidth() <= 64 && isInt<16>(Imm.getSExtValue())) in getIntImmCostIntrin()
218 if ((Idx < 2) || (Imm.getBitWidth() <= 64 && isInt<64>(Imm.getSExtValue()))) in getIntImmCostIntrin()
223 if ((Idx < 4) || (Imm.getBitWidth() <= 64 && isInt<64>(Imm.getSExtValue()))) in getIntImmCostIntrin()
291 if (isInt<16>(Imm.getSExtValue())) in getIntImmCostInst()

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