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Searched refs:getRegClasses (Results 1 – 7 of 7) sorted by relevance

/freebsd-14.2/contrib/llvm-project/llvm/utils/TableGen/
H A DRegisterBankEmitter.cpp185 for (const auto &PossibleSubclass : RegisterClassHierarchy.getRegClasses()) { in visitRegisterBankClasses()
202 BitVector BV(RegisterClassHierarchy.getRegClasses().size()); in visitRegisterBankClasses()
224 (RegisterClassHierarchy.getRegClasses().size() + 31) / 32); in emitBaseClassImplementation()
251 << RegisterClassHierarchy.getRegClasses().size() << ");\n"; in emitBaseClassImplementation()
320 for (const auto &Class : RegisterClassHierarchy.getRegClasses()) { in run()
H A DCodeGenTarget.cpp319 auto &RegClasses = RegBank->getRegClasses(); in getRegNamespace()
382 auto &RegClasses = RegBank.getRegClasses(); in getSuperRegForSubReg()
444 for (const auto &RC : getRegBank().getRegClasses()) { in getRegisterVTs()
459 for (const auto &RC : getRegBank().getRegClasses()) in ReadLegalValueTypes()
H A DRegisterInfoEmitter.cpp137 const auto &RegisterClasses = Bank.getRegClasses(); in runEnums()
211 unsigned NumRCs = RegBank.getRegClasses().size(); in EmitRegUnitPressure()
218 for (const auto &RC : RegBank.getRegClasses()) { in EmitRegUnitPressure()
1015 const auto &RegisterClasses = RegBank.getRegClasses(); in runMCDesc()
1176 const auto &RegisterClasses = RegBank.getRegClasses(); in runTargetHeader()
1217 const auto &RegisterClasses = RegBank.getRegClasses(); in runTargetDesc()
1835 for (const CodeGenRegisterClass &RC : RegBank.getRegClasses()) { in debugDump()
1856 for (const CodeGenRegisterClass &SRC : RegBank.getRegClasses()) { in debugDump()
H A DCodeGenRegisters.h755 std::list<CodeGenRegisterClass> &getRegClasses() { return RegClasses; } in getRegClasses() function
757 const std::list<CodeGenRegisterClass> &getRegClasses() const { in getRegClasses() function
H A DCodeGenRegisters.cpp987 auto &RegClasses = RegBank.getRegClasses(); in computeSubClasses()
1050 auto &RegClasses = RegBank.getRegClasses(); in getMatchingSubClassWithSubRegs()
1693 for (auto &RegClass : RegBank.getRegClasses()) { in computeUberSets()
1977 auto &RegClasses = getRegClasses(); in computeRegUnitSets()
2438 for (const auto &RC : getRegClasses()) { in getRegClassForRegister()
2479 for (const auto &RC : getRegClasses()) { in getMinimalPhysRegClass()
H A DDAGISelMatcherGen.cpp33 for (const auto &RC : T.getRegBank().getRegClasses()) { in getRegisterValueType()
H A DAsmMatcherEmitter.cpp1227 auto &RegClassList = Target.getRegBank().getRegClasses(); in buildRegisterClasses()