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Searched refs:getRegClassForTypeOnBank (Results 1 – 6 of 6) sorted by relevance

/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsInstructionSelector.cpp49 getRegClassForTypeOnBank(Register Reg, MachineRegisterInfo &MRI) const;
111 const TargetRegisterClass *RC = getRegClassForTypeOnBank(DstReg, MRI); in selectCopy()
120 const TargetRegisterClass *MipsInstructionSelector::getRegClassForTypeOnBank( in getRegClassForTypeOnBank() function in MipsInstructionSelector
433 DefRC = getRegClassForTypeOnBank(DestReg, MRI); in select()
580 MRI.setRegClass(Dst, getRegClassForTypeOnBank(Dst, MRI)); in select()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/RISCV/GISel/
H A DRISCVInstructionSelector.cpp50 getRegClassForTypeOnBank(LLT Ty, const RegisterBank &RB) const;
523 DefRC = getRegClassForTypeOnBank(DefTy, RB); in select()
833 const TargetRegisterClass *RISCVInstructionSelector::getRegClassForTypeOnBank( in getRegClassForTypeOnBank() function in RISCVInstructionSelector
868 const TargetRegisterClass *DstRC = getRegClassForTypeOnBank( in selectCopy()
891 const TargetRegisterClass *DstRC = getRegClassForTypeOnBank( in selectImplicitDef()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/
H A DAArch64InstructionSelector.cpp562 getRegClassForTypeOnBank(LLT Ty, const RegisterBank &RB, in getRegClassForTypeOnBank() function
977 RC = getRegClassForTypeOnBank(Ty, RB); in selectDebugInstr()
2462 DefRC = getRegClassForTypeOnBank(DefTy, RB); in select()
2942 auto *RC = getRegClassForTypeOnBank(MemTy, RB); in select()
2958 auto *RC = getRegClassForTypeOnBank(MemTy, RB); in select()
3855 getRegClassForTypeOnBank(SrcTy, VecRB, true); in selectVectorICmp()
4048 getRegClassForTypeOnBank(ScalarTy, DstRB, true); in emitExtractVectorElt()
4057 getRegClassForTypeOnBank(VecTy, VecRB, true); in emitExtractVectorElt()
4216 const TargetRegisterClass *RC = getRegClassForTypeOnBank( in selectUnmergeValues()
4669 getRegClassForTypeOnBank(Op1Ty.multiplyElements(2), FPRBank); in emitVectorConcat()
[all …]
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIRegisterInfo.h337 getRegClassForTypeOnBank(LLT Ty, const RegisterBank &Bank) const { in getRegClassForTypeOnBank() function
H A DAMDGPUInstructionSelector.cpp236 DefRC = TRI.getRegClassForTypeOnBank(DefTy, RB); in selectPHI()
2418 TRI.getRegClassForTypeOnBank(SrcTy, *SrcBank); in selectG_SZA_EXT()
2988 const TargetRegisterClass *DstRC = TRI.getRegClassForTypeOnBank(Ty, *DstRB); in selectG_PTRMASK()
2989 const TargetRegisterClass *SrcRC = TRI.getRegClassForTypeOnBank(Ty, *SrcRB); in selectG_PTRMASK()
2991 TRI.getRegClassForTypeOnBank(MaskTy, *MaskRB); in selectG_PTRMASK()
3107 TRI.getRegClassForTypeOnBank(SrcTy, *SrcRB); in selectG_EXTRACT_VECTOR_ELT()
3109 TRI.getRegClassForTypeOnBank(DstTy, *DstRB); in selectG_EXTRACT_VECTOR_ELT()
3189 TRI.getRegClassForTypeOnBank(VecTy, *VecRB); in selectG_INSERT_VECTOR_ELT()
3191 TRI.getRegClassForTypeOnBank(ValTy, *ValRB); in selectG_INSERT_VECTOR_ELT()
H A DSIRegisterInfo.cpp3109 return getRegClassForTypeOnBank(MRI.getType(MO.getReg()), *RB); in getConstrainedRegClassForOperand()