Home
last modified time | relevance | path

Searched refs:getRegClass (Results 1 – 25 of 215) sorted by relevance

123456789

/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsOptionRecord.h47 GPR32RegClass = &(TRI->getRegClass(Mips::GPR32RegClassID)); in MipsRegInfoRecord()
48 GPR64RegClass = &(TRI->getRegClass(Mips::GPR64RegClassID)); in MipsRegInfoRecord()
49 FGR32RegClass = &(TRI->getRegClass(Mips::FGR32RegClassID)); in MipsRegInfoRecord()
50 FGR64RegClass = &(TRI->getRegClass(Mips::FGR64RegClassID)); in MipsRegInfoRecord()
51 AFGR64RegClass = &(TRI->getRegClass(Mips::AFGR64RegClassID)); in MipsRegInfoRecord()
52 MSA128BRegClass = &(TRI->getRegClass(Mips::MSA128BRegClassID)); in MipsRegInfoRecord()
53 COP0RegClass = &(TRI->getRegClass(Mips::COP0RegClassID)); in MipsRegInfoRecord()
54 COP2RegClass = &(TRI->getRegClass(Mips::COP2RegClassID)); in MipsRegInfoRecord()
55 COP3RegClass = &(TRI->getRegClass(Mips::COP3RegClassID)); in MipsRegInfoRecord()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AMDGPU/MCTargetDesc/
H A DAMDGPUMCCodeEmitter.cpp505 if (MRI.getRegClass(AMDGPU::AGPR_32RegClassID).contains(Reg) || in getAVOperandEncoding()
506 MRI.getRegClass(AMDGPU::AReg_64RegClassID).contains(Reg) || in getAVOperandEncoding()
507 MRI.getRegClass(AMDGPU::AReg_96RegClassID).contains(Reg) || in getAVOperandEncoding()
508 MRI.getRegClass(AMDGPU::AReg_128RegClassID).contains(Reg) || in getAVOperandEncoding()
509 MRI.getRegClass(AMDGPU::AReg_160RegClassID).contains(Reg) || in getAVOperandEncoding()
510 MRI.getRegClass(AMDGPU::AReg_192RegClassID).contains(Reg) || in getAVOperandEncoding()
511 MRI.getRegClass(AMDGPU::AReg_224RegClassID).contains(Reg) || in getAVOperandEncoding()
512 MRI.getRegClass(AMDGPU::AReg_256RegClassID).contains(Reg) || in getAVOperandEncoding()
513 MRI.getRegClass(AMDGPU::AReg_288RegClassID).contains(Reg) || in getAVOperandEncoding()
514 MRI.getRegClass(AMDGPU::AReg_320RegClassID).contains(Reg) || in getAVOperandEncoding()
[all …]
/freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/
H A DRegisterBank.cpp26 const TargetRegisterClass &RC = *TRI.getRegClass(RCId); in verify()
37 const TargetRegisterClass &SubRC = *TRI.getRegClass(RCId); in verify()
92 const TargetRegisterClass &RC = *TRI->getRegClass(RCId); in print()
H A DRegAllocBase.cpp106 << TRI->getRegClassName(MRI->getRegClass(VirtReg->reg())) in allocatePhysRegs()
127 const TargetRegisterClass *RC = MRI->getRegClass(VirtReg->reg()); in allocatePhysRegs()
184 const TargetRegisterClass &RC = *MRI->getRegClass(Reg); in enqueue()
H A DPeepholeOptimizer.cpp520 const TargetRegisterClass *DstRC = MRI->getRegClass(DstReg); in INITIALIZE_PASS_DEPENDENCY()
531 TRI->getSubClassWithSubReg(MRI->getRegClass(SrcReg), SubIdx) != nullptr; in INITIALIZE_PASS_DEPENDENCY()
617 const TargetRegisterClass *RC = MRI->getRegClass(SrcReg); in INITIALIZE_PASS_DEPENDENCY()
646 RC = MRI->getRegClass(UseMI->getOperand(0).getReg()); in INITIALIZE_PASS_DEPENDENCY()
732 const TargetRegisterClass *DefRC = MRI->getRegClass(Reg); in findNextSource()
794 const TargetRegisterClass *SrcRC = MRI->getRegClass(CurSrcPair.Reg); in findNextSource()
824 const TargetRegisterClass *NewRC = MRI.getRegClass(SrcRegs[0].Reg); in insertPHI()
1294 const TargetRegisterClass *DefRC = MRI->getRegClass(Def.Reg); in rewriteSource()
1440 MRI->getRegClass(DstReg) == MRI->getRegClass(Reg)) { in foldImmediate()
1493 if (MRI->getRegClass(DstReg) != MRI->getRegClass(PrevDstReg)) in foldRedundantCopy()
[all …]
H A DRegAllocFast.cpp420 const TargetRegisterClass &RC = *MRI->getRegClass(Reg); in shouldAllocateRegister()
447 const TargetRegisterClass &RC = *MRI->getRegClass(VirtReg); in getStackSpaceFor()
546 const TargetRegisterClass &RC = *MRI->getRegClass(VirtReg); in spill()
604 const TargetRegisterClass &RC = *MRI->getRegClass(VirtReg); in reload()
869 const TargetRegisterClass &RC = *MRI->getRegClass(VirtReg); in allocVirtReg()
965 const TargetRegisterClass &RC = *MRI->getRegClass(VirtReg); in allocVirtRegUndef()
1043 const TargetRegisterClass &RC = *MRI->getRegClass(VirtReg); in defineVirtReg()
1245 const TargetRegisterClass *OpRC = MRI->getRegClass(Reg); in addRegClassDefCounts()
1259 const TargetRegisterClass *IdxRC = TRI->getRegClass(RCIdx); in addRegClassDefCounts()
1305 const TargetRegisterClass &RC0 = *MRI->getRegClass(Reg0); in findAndSortDefOperandIndexes()
[all …]
H A DDetectDeadLanes.cpp73 const TargetRegisterClass *SrcRC = MRI.getRegClass(SrcReg); in isCrossCopy()
170 const TargetRegisterClass *RC = MRI->getRegClass(DefReg); in transferUsedLanes()
289 const TargetRegisterClass *DefRC = MRI->getRegClass(Reg); in determineInitialDefinedLanes()
354 const TargetRegisterClass *DstRC = MRI->getRegClass(DefReg); in determineInitialUsedLanes()
447 const TargetRegisterClass *DstRC = MRI->getRegClass(DefReg); in isUndefInput()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyPeephole.cpp67 Register NewReg = MRI.createVirtualRegister(MRI.getRegClass(OldReg)); in maybeRewriteToDrop()
98 const TargetRegisterClass *RegClass = MRI.getRegClass(Reg); in maybeRewriteToFallthrough()
149 if (MRI.getRegClass(NewReg) != MRI.getRegClass(OldReg)) in runOnMachineFunction()
H A DWebAssemblyExplicitLocals.cpp301 const TargetRegisterClass *RC = MRI.getRegClass(DefReg); in runOnMachineFunction()
334 const TargetRegisterClass *RC = MRI.getRegClass(OldReg); in runOnMachineFunction()
406 const TargetRegisterClass *RC = MRI.getRegClass(OldReg); in runOnMachineFunction()
442 typeForRegClass(MRI.getRegClass(Reg))); in runOnMachineFunction()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMRegisterBankInfo.cpp147 assert(RBGPR.covers(*TRI.getRegClass(ARM::GPRRegClassID)) && in ARMRegisterBankInfo()
149 assert(RBGPR.covers(*TRI.getRegClass(ARM::GPRwithAPSRRegClassID)) && in ARMRegisterBankInfo()
151 assert(RBGPR.covers(*TRI.getRegClass(ARM::GPRnopcRegClassID)) && in ARMRegisterBankInfo()
153 assert(RBGPR.covers(*TRI.getRegClass(ARM::rGPRRegClassID)) && in ARMRegisterBankInfo()
155 assert(RBGPR.covers(*TRI.getRegClass(ARM::tGPRRegClassID)) && in ARMRegisterBankInfo()
157 assert(RBGPR.covers(*TRI.getRegClass(ARM::tcGPRRegClassID)) && in ARMRegisterBankInfo()
159 assert(RBGPR.covers(*TRI.getRegClass(ARM::GPRnoip_and_tcGPRRegClassID)) && in ARMRegisterBankInfo()
161 assert(RBGPR.covers(*TRI.getRegClass( in ARMRegisterBankInfo()
164 assert(RBGPR.covers(*TRI.getRegClass(ARM::tGPROdd_and_tcGPRRegClassID)) && in ARMRegisterBankInfo()
H A DA15SDOptimizer.cpp139 return MRI->getRegClass(Reg)->hasSuperClassEq(TRC); in usesRegClass()
270 MRI->getRegClass(MI->getOperand(1).getReg()); in optimizeSDPattern()
271 if (TRC->hasSuperClassEq(MRI->getRegClass(FullReg))) { in optimizeSDPattern()
514 if (MRI->getRegClass(Reg)->hasSuperClassEq(&ARM::QPRRegClass) || in optimizeAllLanesPattern()
515 MRI->getRegClass(Reg)->hasSuperClassEq(&ARM::DPairRegClass)) { in optimizeAllLanesPattern()
531 } else if (MRI->getRegClass(Reg)->hasSuperClassEq(&ARM::DPRRegClass)) { in optimizeAllLanesPattern()
537 assert(MRI->getRegClass(Reg)->hasSuperClassEq(&ARM::SPRRegClass) && in optimizeAllLanesPattern()
635 MRI->constrainRegClass(NewReg, MRI->getRegClass(Use->getReg())); in runOnInstruction()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64MIPeepholeOpt.cpp251 MRI->getRegClass(SrcMI->getOperand(1).getReg()); in visitORR()
296 const TargetRegisterClass *RC = MRI->getRegClass(DstReg); in visitINSERT()
519 TII->getRegClass(TII->get(Opcode.first), 0, TRI, *MF); in splitTwoPartImm()
521 TII->getRegClass(TII->get(Opcode.first), 1, TRI, *MF); in splitTwoPartImm()
525 : TII->getRegClass(TII->get(Opcode.second), 0, TRI, *MF); in splitTwoPartImm()
529 : TII->getRegClass(TII->get(Opcode.second), 1, TRI, *MF); in splitTwoPartImm()
545 MRI->constrainRegClass(NewDstReg, MRI->getRegClass(DstReg)); in splitTwoPartImm()
589 if (MRI->getRegClass(SrcMI->getOperand(1).getReg()) == in visitINSviGPR()
617 const TargetRegisterClass *RC = MRI->getRegClass(MI->getOperand(0).getReg()); in is64bitDefwithZeroHigh64bit()
666 MRI->constrainRegClass(NewDef, MRI->getRegClass(OldDef)); in visitINSvi64lane()
H A DAArch64AdvSIMDScalarPass.cpp109 return MRI->getRegClass(Reg)->hasSuperClassEq(&AArch64::GPR64RegClass); in isGPR64()
116 return (MRI->getRegClass(Reg)->hasSuperClassEq(&AArch64::FPR64RegClass) && in isFPR64()
118 (MRI->getRegClass(Reg)->hasSuperClassEq(&AArch64::FPR128RegClass) && in isFPR64()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86TileConfig.cpp118 unsigned AMXRegNum = TRI->getRegClass(X86::TILERegClassID)->getNumRegs(); in INITIALIZE_PASS_DEPENDENCY()
124 if (MRI.getRegClass(VirtReg)->getID() != X86::TILERegClassID) in INITIALIZE_PASS_DEPENDENCY()
179 unsigned RegSize = TRI->getRegSizeInBits(*MRI.getRegClass(R)); in INITIALIZE_PASS_DEPENDENCY()
H A DX86FastPreTileConfig.cpp126 const TargetRegisterClass &RC = *MRI->getRegClass(VirtReg); in getStackSpaceFor()
207 const TargetRegisterClass &RC = *MRI->getRegClass(VirtReg); in spill()
222 const TargetRegisterClass &RC = *MRI->getRegClass(OrigReg); in reload()
282 MRI->getRegClass(Reg)->getID() == X86::TILERegClassID) in isTileDef()
428 MRI->getRegClass(MO.getReg())->getID() == X86::TILERegClassID) in isTileRegDef()
528 MRI->getRegClass(Reg)->getID() == X86::TILERegClassID) in configBasicBlock()
670 if (MRI->getRegClass(VirtReg)->getID() == X86::TILERegClassID) { in runOnMachineFunction()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DGCNPreRAOptimizations.cpp91 bool IsAGPRDst = TRI->isAGPRClass(MRI->getRegClass(Reg)); in processReg()
113 bool IsAGPRSrc = TRI->isAGPRClass(MRI->getRegClass(SrcReg)); in processReg()
231 const TargetRegisterClass *RC = MRI->getRegClass(Reg); in runOnMachineFunction()
H A DSIFixSGPRCopies.cpp196 ? MRI.getRegClass(SrcReg) in getCopyRegClasses()
203 ? MRI.getRegClass(DstReg) in getCopyRegClasses()
247 MRI.setRegClass(DstReg, TRI->getEquivalentSGPRClass(MRI.getRegClass(DstReg))); in tryChangeVGPRtoSGPRinCopy()
271 if (!TRI->isSGPRClass(MRI.getRegClass(DstReg))) in foldVGPRCopyIntoRegSequence()
662 const TargetRegisterClass *SrcRC = MRI->getRegClass(MO.getReg()); in runOnMachineFunction()
820 const TargetRegisterClass *RC0 = MRI->getRegClass(PHIRes); in processPHINode()
857 MRI->getRegClass(MaybeVGPRConstMO.getReg()); in tryMoveVGPRConstToSGPR()
879 TRI->hasVectorRegisters(MRI->getRegClass(SrcReg))) { in lowerSpecialCase()
915 const TargetRegisterClass *DstRC = MRI->getRegClass(DstReg); in analyzeVGPRToSGPRCopy()
1112 TRI->getRegClass(AMDGPU::SReg_1_XEXECRegClassID)); in fixSCCCopies()
H A DGCNRewritePartialRegUses.cpp210 auto *RC = TRI->getRegClass(ClassID); in getAllocatableAndAlignedRegClassMask()
271 auto *RC = TRI->getRegClass(ClassID); in getRegClassWithShiftedSubregs()
407 return TII->getRegClass(TII->get(MI->getOpcode()), MI->getOperandNo(&MO), TRI, in getOperandRegClass()
418 auto *RC = MRI->getRegClass(Reg); in rewriteReg()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVRVVInitUndef.cpp110 const TargetRegisterClass *RC = MRI->getRegClass(R); in isVectorRegClass()
186 getVRLargestSuperClass(MRI->getRegClass(Reg)); in handleSubReg()
233 getVRLargestSuperClass(MRI->getRegClass(MO.getReg())); in fixupIllOperand()
257 TII->getRegClass(MI.getDesc(), UseOpIdx, TRI, MF); in processBasicBlock()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCVSXFMAMutate.cpp132 if (MRI.getRegClass(AddendMI->getOperand(0).getReg()) != in processBlock()
133 MRI.getRegClass(AddendSrcReg)) in processBlock()
138 if (!MRI.getRegClass(AddendMI->getOperand(0).getReg()) in processBlock()
238 MRI.getRegClass(OldFMAReg))) in processBlock()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/X86/GISel/
H A DX86InstructionSelector.cpp133 const TargetRegisterClass *getRegClass(LLT Ty, unsigned Reg,
204 X86InstructionSelector::getRegClass(LLT Ty, unsigned Reg, in getRegClass() function in X86InstructionSelector
207 return getRegClass(Ty, RegBank); in getRegClass()
256 RC = getRegClass(Ty, RB); in selectDebugInstr()
287 getRegClass(MRI.getType(SrcReg), SrcRegBank); in selectCopy()
317 getRegClass(MRI.getType(DstReg), DstRegBank); in selectCopy()
777 const TargetRegisterClass *DstRC = getRegClass(DstTy, DstRB); in selectTruncOrPtrToInt()
778 const TargetRegisterClass *SrcRC = getRegClass(SrcTy, SrcRB); in selectTruncOrPtrToInt()
906 const TargetRegisterClass *DstRC = getRegClass(DstTy, DstRB); in selectAnyext()
907 const TargetRegisterClass *SrcRC = getRegClass(SrcTy, SrcRB); in selectAnyext()
[all …]
/freebsd-14.2/contrib/llvm-project/llvm/include/llvm/IR/
H A DInlineAsm.h315 unsigned getRegClass() const { return Bitfield::get<RegClass>(Storage); } in getRegClass() function
377 if (!getRegClass()) in hasRegClassConstraint()
379 RC = getRegClass() - 1; in hasRegClassConstraint()
403 assert(getRegClass() == 0 && "Register class already set"); in setRegClass()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AArch64/MCTargetDesc/
H A DAArch64InstPrinter.cpp866 if (MRI.getRegClass(AArch64::GPR32RegClassID).contains(Rm)) in printRangePrefetchAlias()
1659 if (MRI.getRegClass(AArch64::DDRegClassID).contains(Reg) || in printVectorList()
1660 MRI.getRegClass(AArch64::ZPR2RegClassID).contains(Reg) || in printVectorList()
1661 MRI.getRegClass(AArch64::QQRegClassID).contains(Reg) || in printVectorList()
1662 MRI.getRegClass(AArch64::PPR2RegClassID).contains(Reg) || in printVectorList()
1667 MRI.getRegClass(AArch64::QQQRegClassID).contains(Reg)) in printVectorList()
1693 if (MRI.getRegClass(AArch64::FPR64RegClassID).contains(Reg)) { in printVectorList()
1695 MRI.getRegClass(AArch64::FPR128RegClassID); in printVectorList()
1699 if ((MRI.getRegClass(AArch64::ZPRRegClassID).contains(Reg) || in printVectorList()
1700 MRI.getRegClass(AArch64::PPRRegClassID).contains(Reg)) && in printVectorList()
[all …]
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonGenPredicate.cpp140 const TargetRegisterClass *RC = MRI->getRegClass(R); in INITIALIZE_PASS_DEPENDENCY()
335 if (MRI->getRegClass(PR.R) != PredRC) in isScalarPred()
434 const TargetRegisterClass *RC = MRI->getRegClass(OutR.R); in convertToPredForm()
478 if (MRI->getRegClass(DR.R) != PredRC) in eliminatePredCopies()
480 if (MRI->getRegClass(SR.R) != PredRC) in eliminatePredCopies()
/freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DInstrEmitter.cpp134 TII->getRegClass(II, i + II.getNumDefs(), TRI, *MF)); in EmitCopyFromReg()
159 DstRC = MRI->getRegClass(VRBase); in EmitCopyFromReg()
206 TRI->getAllocatableClass(TII->getRegClass(II, i, TRI, *MF)); in CreateVirtualRegisters()
235 const TargetRegisterClass *RegRC = MRI->getRegClass(Reg); in CreateVirtualRegisters()
316 OpRC = TII->getRegClass(*II, IIOpNum, TRI, *MF); in AddRegisterOperand()
451 const TargetRegisterClass *VRC = MRI->getRegClass(VReg); in ConstrainForSubReg()
518 TRC == MRI->getRegClass(SrcReg)) { in EmitSubregNode()
575 if (VRBase == 0 || !SRC->hasSubClassEq(MRI->getRegClass(VRBase))) in EmitSubregNode()
616 TRI->getAllocatableClass(TRI->getRegClass(DstRCIdx)); in EmitCopyToRegClassNode()
633 const TargetRegisterClass *RC = TRI->getRegClass(DstRCIdx); in EmitRegSequence()
[all …]

123456789