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Searched refs:getRegBank (Results 1 – 25 of 39) sorted by relevance

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/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/
H A DAArch64RegisterBankInfo.cpp56 const RegisterBank &RBGPR = getRegBank(AArch64::GPRRegBankID); in AArch64RegisterBankInfo()
61 const RegisterBank &RBFPR = getRegBank(AArch64::FPRRegBankID); in AArch64RegisterBankInfo()
66 const RegisterBank &RBCCR = getRegBank(AArch64::CCRegBankID); in AArch64RegisterBankInfo()
259 return getRegBank(AArch64::FPRRegBankID); in getRegBankFromRegClass()
283 return getRegBank(AArch64::GPRRegBankID); in getRegBankFromRegClass()
285 return getRegBank(AArch64::CCRegBankID); in getRegBankFromRegClass()
540 auto *RB = getRegBank(MI.getOperand(0).getReg(), MRI, TRI); in hasFPConstraints()
716 const RegisterBank *DstRB = getRegBank(DstReg, MRI, TRI); in getInstrMapping()
717 const RegisterBank *SrcRB = getRegBank(SrcReg, MRI, TRI); in getInstrMapping()
812 if (getRegBank(SrcReg, MRI, TRI) == &AArch64::FPRRegBank) in getInstrMapping()
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H A DAArch64InstructionSelector.cpp1162 assert(RBI.getRegBank(False, MRI, TRI)->getID() == in emitSelect()
1163 RBI.getRegBank(True, MRI, TRI)->getID() && in emitSelect()
1651 assert(RBI.getRegBank(CompareReg, MRI, TRI)->getID() == in emitCBZ()
2242 if (RBI.getRegBank(StoreSrcReg, MRI, TRI) == in contractCrossBankCopyIntoStore()
2243 RBI.getRegBank(DefDstReg, MRI, TRI)) in contractCrossBankCopyIntoStore()
2621 const RegisterBank &RB = *RBI.getRegBank(DefReg, MRI, TRI); in select()
2935 const RegisterBank &RB = *RBI.getRegBank(ValReg, MRI, TRI); in select()
3317 assert((*RBI.getRegBank(DefReg, MRI, TRI)).getID() == in select()
4150 *RBI.getRegBank(I.getOperand(0).getReg(), MRI, TRI); in selectSplitVectorUnmerge()
4218 *RBI.getRegBank(SrcReg, MRI, TRI)); in selectUnmergeValues()
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/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/PowerPC/GISel/
H A DPPCRegisterBankInfo.cpp42 return getRegBank(PPC::GPRRegBankID); in getRegBankFromRegClass()
51 return getRegBank(PPC::FPRRegBankID); in getRegBankFromRegClass()
59 return getRegBank(PPC::VECRegBankID); in getRegBankFromRegClass()
62 return getRegBank(PPC::CRRegBankID); in getRegBankFromRegClass()
310 auto *RB = getRegBank(MI.getOperand(0).getReg(), MRI, TRI); in hasFPConstraints()
H A DPPCInstructionSelector.cpp138 const RegisterBank *DstRegBank = RBI.getRegBank(DstReg, MRI, TRI); in selectCopy()
245 const RegisterBank *DstRegBank = RBI.getRegBank(DstReg, MRI, TRI); in selectZExt()
741 I.getOpcode(), RBI.getRegBank(LdSt.getReg(0), MRI, TRI)->getID(), in select()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMInstructionSelector.cpp189 const RegisterBank *RegBank = RBI.getRegBank(Reg, MRI, TRI); in guessRegClass()
243 RBI.getRegBank(VReg0, MRI, TRI)->getID() == ARM::FPRRegBankID && in selectMergeValues()
248 RBI.getRegBank(VReg1, MRI, TRI)->getID() == ARM::GPRRegBankID && in selectMergeValues()
253 RBI.getRegBank(VReg2, MRI, TRI)->getID() == ARM::GPRRegBankID && in selectMergeValues()
275 RBI.getRegBank(VReg0, MRI, TRI)->getID() == ARM::GPRRegBankID && in selectUnmergeValues()
518 if (RBI.getRegBank(Reg, MRI, TRI)->getID() != ExpectedRegBankID) { in validReg()
919 const auto &SrcRegBank = *RBI.getRegBank(SrcReg, MRI, TRI); in select()
920 const auto &DstRegBank = *RBI.getRegBank(DstReg, MRI, TRI); in select()
1014 const auto &SrcRegBank = *RBI.getRegBank(SrcReg, MRI, TRI); in select()
1015 const auto &DstRegBank = *RBI.getRegBank(DstReg, MRI, TRI); in select()
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H A DARMRegisterBankInfo.cpp142 const RegisterBank &RBGPR = getRegBank(ARM::GPRRegBankID); in ARMRegisterBankInfo()
201 return getRegBank(ARM::GPRRegBankID); in getRegBankFromRegClass()
208 return getRegBank(ARM::FPRRegBankID); in getRegBankFromRegClass()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/RISCV/GISel/
H A DRISCVRegisterBankInfo.cpp96 return getRegBank(RISCV::GPRBRegBankID); in getRegBankFromRegClass()
102 return getRegBank(RISCV::FPRBRegBankID); in getRegBankFromRegClass()
116 return getRegBank(RISCV::VRBRegBankID); in getRegBankFromRegClass()
178 return getRegBank(MI.getOperand(0).getReg(), MRI, TRI) == &RISCV::FPRBRegBank; in hasFPConstraints()
385 if (getRegBank(VReg, MRI, TRI) == &RISCV::FPRBRegBank || in getInstrMapping()
H A DRISCVInstructionSelector.cpp751 MRI.setRegBank(PtrToInt.getReg(0), RBI.getRegBank(RISCV::GPRBRegBankID)); in replacePtrWithInt()
853 return RBI.getRegBank(Reg, MRI, TRI)->getID() == RISCV::GPRBRegBankID; in isRegInGprb()
858 return RBI.getRegBank(Reg, MRI, TRI)->getID() == RISCV::FPRBRegBankID; in isRegInFprb()
869 MRI.getType(DstReg), *RBI.getRegBank(DstReg, MRI, TRI)); in selectCopy()
892 MRI.getType(DstReg), *RBI.getRegBank(DstReg, MRI, TRI)); in selectImplicitDef()
1104 if (RBI.getRegBank(DstReg, MRI, TRI)->getID() == RISCV::FPRBRegBankID) { in selectSelect()
/freebsd-14.2/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DRegisterBankInfo.h440 const RegisterBank &getRegBank(unsigned ID) { in getRegBank() function
585 const RegisterBank &getRegBank(unsigned ID) const { in getRegBank() function
586 return const_cast<RegisterBankInfo *>(this)->getRegBank(ID); in getRegBank()
599 const RegisterBank *getRegBank(Register Reg, const MachineRegisterInfo &MRI,
/freebsd-14.2/contrib/llvm-project/llvm/utils/TableGen/
H A DCodeGenTarget.cpp372 CodeGenRegBank &CodeGenTarget::getRegBank() const { in getRegBank() function in CodeGenTarget
433 return getRegBank().getRegistersByName().lookup(Name); in getRegisterByName()
437 return *getRegBank().getRegClass(R); in getRegisterClass()
442 const CodeGenRegister *Reg = getRegBank().getReg(R); in getRegisterVTs()
444 for (const auto &RC : getRegBank().getRegClasses()) { in getRegisterVTs()
459 for (const auto &RC : getRegBank().getRegClasses()) in ReadLegalValueTypes()
H A DDAGISelMatcherGen.cpp31 const CodeGenRegister *Reg = T.getRegBank().getReg(R); in getRegisterValueType()
33 for (const auto &RC : T.getRegBank().getRegClasses()) { in getRegisterValueType()
680 CGP.getTargetInfo().getRegBank().getReg(Def); in EmitResultLeafAsOperand()
726 const CodeGenRegBank &RB = CGP.getTargetInfo().getRegBank(); in EmitResultLeafAsOperand()
892 CGP.getTargetInfo().getRegBank().getReg(PhysRegInputs[i].first); in EmitResultInstructionAsOperand()
H A DRegisterBankEmitter.cpp217 const CodeGenRegBank &RegisterClassHierarchy = Target.getRegBank(); in emitBaseClassImplementation()
294 const CodeGenRegBank &RegisterClassHierarchy = Target.getRegBank(); in run()
H A DCodeGenTarget.h120 CodeGenRegBank &getRegBank() const;
H A DCodeGenInstAlias.cpp78 T.getRegBank().getReg(ADI->getDef()))) in tryAliasOpMatch()
H A DRegisterInfoEmitter.cpp64 CodeGenRegBank &RegBank = Target.getRegBank(); in RegisterInfoEmitter()
1044 BVE.add(Target.getRegBank().getReg(Reg)->EnumValue); in runMCDesc()
1808 CodeGenRegBank &RegBank = Target.getRegBank(); in run()
1826 CodeGenRegBank &RegBank = Target.getRegBank(); in debugDump()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/X86/GISel/
H A DX86RegisterBankInfo.cpp31 const RegisterBank &RBGPR = getRegBank(X86::GPRRegBankID); in X86RegisterBankInfo()
53 return getRegBank(X86::GPRRegBankID); in getRegBankFromRegClass()
60 return getRegBank(X86::VECRRegBankID); in getRegBankFromRegClass()
H A DX86InstructionSelector.cpp206 const RegisterBank &RegBank = *RBI.getRegBank(Reg, MRI, TRI); in getRegClass()
274 const RegisterBank &DstRegBank = *RBI.getRegBank(DstReg, MRI, TRI); in selectCopy()
559 const RegisterBank &RB = *RBI.getRegBank(DefReg, MRI, TRI); in selectLoadStoreOp()
768 const RegisterBank &DstRB = *RBI.getRegBank(DstReg, MRI, TRI); in selectTruncOrPtrToInt()
769 const RegisterBank &SrcRB = *RBI.getRegBank(SrcReg, MRI, TRI); in selectTruncOrPtrToInt()
897 const RegisterBank &DstRB = *RBI.getRegBank(DstReg, MRI, TRI); in selectAnyext()
898 const RegisterBank &SrcRB = *RBI.getRegBank(SrcReg, MRI, TRI); in selectAnyext()
1135 const RegisterBank &DstRB = *RBI.getRegBank(DstReg, MRI, TRI); in selectUAddSub()
1419 const RegisterBank &RegBank = *RBI.getRegBank(DstReg, MRI, TRI); in selectMergeValues()
1488 const RegisterBank &RegBank = *RBI.getRegBank(DstReg, MRI, TRI); in materializeFP()
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/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsRegisterBankInfo.cpp92 return getRegBank(Mips::GPRBRegBankID); in getRegBankFromRegClass()
101 return getRegBank(Mips::FPRBRegBankID); in getRegBankFromRegClass()
372 RBI.getRegBank(CopyInst->getOperand(Op).getReg(), MRI, TRI); in setTypesAccordingToPhysicalRegister()
708 MRI.setRegBank(Dest, getRegBank(Mips::GPRBRegBankID)); in setRegBank()
713 MRI.setRegBank(Dest, getRegBank(Mips::GPRBRegBankID)); in setRegBank()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUInstructionSelector.cpp300 const RegisterBank *DstRB = RBI.getRegBank(DstReg, *MRI, TRI); in selectG_AND_OR_XOR()
327 const RegisterBank *DstRB = RBI.getRegBank(DstReg, *MRI, TRI); in selectG_ADD_SUB()
523 const RegisterBank *SrcBank = RBI.getRegBank(SrcReg, *MRI, TRI); in selectG_EXTRACT()
555 const RegisterBank *DstBank = RBI.getRegBank(DstReg, *MRI, TRI); in selectG_MERGE_VALUES()
597 const RegisterBank *SrcBank = RBI.getRegBank(SrcReg, *MRI, TRI); in selectG_UNMERGE_VALUES()
650 const RegisterBank *DstBank = RBI.getRegBank(Dst, *MRI, TRI); in selectG_BUILD_VECTOR()
1501 const RegisterBank *DstRB = RBI.getRegBank(DstReg, *MRI, TRI); in selectGroupStaticSize()
2260 DstRB = RBI.getRegBank(DstReg, *MRI, TRI); in selectG_TRUNC()
2559 const RegisterBank *DstRB = RBI.getRegBank(Dst, *MRI, TRI); in selectG_FPEXT()
2675 const RegisterBank *DstRB = RBI.getRegBank(Dst, *MRI, TRI); in selectG_FNEG()
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H A DAMDGPURegisterBankInfo.cpp668 const RegisterBank *Bank = getRegBank(Reg, *MRI, *TRI); in split64BitValueForMapping()
707 const RegisterBank *Bank = getRegBank(Src, MRI, *TRI); in buildReadFirstLane()
991 const RegisterBank *OpBank = getRegBank(Reg, MRI, *TRI); in collectWaterfallOperands()
1019 const RegisterBank *Bank = getRegBank(Reg, MRI, *TRI); in constrainOpWithReadfirstlane()
1276 if (getRegBank(Base, *MRI, *TRI) == &AMDGPU::VGPRRegBank) { in setBufferOffsets()
3631 const RegisterBank *PtrBank = getRegBank(PtrReg, MRI, *TRI); in getValueMappingForPtr()
3686 const RegisterBank *Bank = getRegBank(Reg, MRI, *TRI); in getRegBankID()
3795 const RegisterBank *Bank = getRegBank(Reg, MRI, *TRI); in getInstrMapping()
3813 getValueMapping(0, Size, getRegBank(ResultBank)); in getInstrMapping()
3836 = getRegBank(MI.getOperand(0).getReg(), MRI, *TRI); in getInstrMapping()
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H A DAMDGPURegBankCombiner.cpp129 return RBI.getRegBank(Reg, MRI, TRI)->getID() == AMDGPU::VGPRRegBankID; in isVgprRegBank()
145 MRI.setRegBank(VgprReg, RBI.getRegBank(AMDGPU::VGPRRegBankID)); in getAsVgpr()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/M68k/GISel/
H A DM68kRegisterBankInfo.cpp64 return getRegBank(M68k::GPRRegBankID); in getRegBankFromRegClass()
/freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/
H A DRegisterBankInfo.cpp73 const RegisterBank &RegBank = getRegBank(Idx); in verify()
84 RegisterBankInfo::getRegBank(Register Reg, const MachineRegisterInfo &MRI, in getRegBank() function in RegisterBankInfo
198 const RegisterBank *AltRegBank = getRegBank(Reg, MRI, TRI); in getInstrMappingImpl()
243 const RegisterBank *AltRegBank = getRegBank(Reg, MRI, TRI); in getInstrMappingImpl()
/freebsd-14.2/contrib/llvm-project/llvm/include/llvm/CodeGen/MIRParser/
H A DMIParser.h151 const RegisterBank *getRegBank(StringRef Name);
/freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/
H A DRegBankSelect.cpp120 const RegisterBank *CurRegBank = RBI->getRegBank(Reg, *MRI, *TRI); in assignmentMatch()
244 const RegisterBank *CurRegBank = RBI->getRegBank(MO.getReg(), *MRI, *TRI); in getRepairCost()
644 RBI->getRegBank(MI.getOperand(1).getReg(), *MRI, *TRI); in assignInstr()

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