Searched refs:getPhysRegBaseClass (Results 1 – 11 of 11) sorted by relevance
197 : TRI.getPhysRegBaseClass(SrcReg); in getCopyRegClasses()204 : TRI.getPhysRegBaseClass(DstReg); in getCopyRegClasses()
495 !TRI.getPhysRegBaseClass(Reg)) && in analyzeResourceUsage()
125 const TargetRegisterClass *RC = TRI.getPhysRegBaseClass(SuperReg); in SGPRSpillBuilder()2867 RC = getPhysRegBaseClass(Reg); in isSGPRReg()2993 return Reg.isVirtual() ? MRI.getRegClass(Reg) : getPhysRegBaseClass(Reg); in getRegClassForReg()3201 assert(getRegSizeInBits(*getPhysRegBaseClass(Reg)) <= 32); in get32BitRegister()
349 const TargetRegisterClass *RC = TRI.getPhysRegBaseClass(SuperReg); in PrologEpilogSGPRSpillBuilder()1345 const TargetRegisterClass *RC = TRI->getPhysRegBaseClass(Reg); in processFunctionBeforeFrameFinalized()
1216 if (MO.isDef() && TRI->isSGPRClass(TRI->getPhysRegBaseClass(MO.getReg()))) { in fixSMEMtoVectorWriteHazards()1302 if (MO.isDef() && TRI->isSGPRClass(TRI->getPhysRegBaseClass(MO.getReg()))) in fixVcmpxExecWARHazard()
607 TRI->hasVectorRegisters(TRI->getPhysRegBaseClass(Reg))) { in scanInstructions()
799 const TargetRegisterClass *RC = RI.getPhysRegBaseClass(DestReg); in copyPhysReg()801 const TargetRegisterClass *SrcRC = RI.getPhysRegBaseClass(SrcReg); in copyPhysReg()821 RC = RI.getPhysRegBaseClass(DestReg); in copyPhysReg()823 SrcRC = RI.getPhysRegBaseClass(SrcReg); in copyPhysReg()5496 return RI.getPhysRegBaseClass(Reg); in getOpRegClass()9492 RI.getPhysRegBaseClass(srcOp.getReg()); in getInstructionUniformity()
351 return TRI->getPhysRegBaseClass(Reg); in getOperandRegClass()1517 auto RC = TRI.getPhysRegBaseClass(Reg); in IsCopyFromSGPR()
745 const TargetRegisterClass *RC = TRI->getPhysRegBaseClass(Op.getReg()); in getRegInterval()
15141 Ret.second = TRI->getPhysRegBaseClass(Ret.first); in getRegForInlineAsmConstraint()
713 virtual const TargetRegisterClass *getPhysRegBaseClass(MCRegister Reg) const { in getPhysRegBaseClass() function