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Searched refs:getOpRegClass (Results 1 – 5 of 5) sorted by relevance

/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIInstrInfo.h1083 const TargetRegisterClass *getOpRegClass(const MachineInstr &MI,
1109 return RI.getRegSizeInBits(*getOpRegClass(MI, OpNo)) / 8; in getOpSize()
H A DSIInstrInfo.cpp409 EltSize = TRI->getRegSizeInBits(*getOpRegClass(LdSt, 0)) / 16; in getMemOperandsWithOffsetWidth()
2281 const TargetRegisterClass *EltRC = getOpRegClass(MI, 2); in expandPostRAPseudo()
4769 const TargetRegisterClass *DstRC = getOpRegClass(MI, DstIdx); in verifyInstruction()
6483 if (VRC || !RI.isSGPRClass(getOpRegClass(MI, 0))) { in legalizeOperands()
6486 if (getOpRegClass(MI, 0) == &AMDGPU::VReg_1RegClass) { in legalizeOperands()
6489 VRC = RI.isAGPRClass(getOpRegClass(MI, 0)) in legalizeOperands()
6493 VRC = RI.isAGPRClass(getOpRegClass(MI, 0)) in legalizeOperands()
6523 const TargetRegisterClass *DstRC = getOpRegClass(MI, 0); in legalizeOperands()
8172 if (!RI.hasVectorRegisters(getOpRegClass(UseMI, OpNo))) { in addUsersToMoveToVALUWorklist()
8321 const TargetRegisterClass *NewDstRC = getOpRegClass(Inst, 0); in getDestEquivalentVGPRClass()
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H A DSIFixSGPRCopies.cpp658 if (TRI->isSGPRClass(TII->getOpRegClass(MI, 0))) { in runOnMachineFunction()
H A DSIRegisterInfo.cpp2436 bool IsSALU = isSGPRClass(TII->getOpRegClass(*MI, FIOperandNum)); in eliminateFrameIndex()
H A DSIISelLowering.cpp14852 uint32_t DstSize = TRI.getRegSizeInBits(*TII->getOpRegClass(MI, DstIdx)) / 32; in AddIMGInit()
14857 Register PrevDst = MRI.createVirtualRegister(TII->getOpRegClass(MI, DstIdx)); in AddIMGInit()
14868 NewDst = MRI.createVirtualRegister(TII->getOpRegClass(MI, DstIdx)); in AddIMGInit()