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Searched refs:getNOT (Results 1 – 21 of 21) sorted by relevance

/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/VE/
H A DVECustomDAG.cpp419 return DAG.getNOT(DL, Res, Res.getValueType()); in getConstantMask()
/freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DTargetLowering.cpp1594 SDValue New = TLO.DAG.getNOT(dl, Op0, VT); in SimplifyDemandedBits()
5207 SDValue Not = DAG.getNOT(dl, N1, OpVT); in SimplifySetCC()
5312 N0 = DAG.getNOT(dl, Temp, OpVT); in SimplifySetCC()
5321 Temp = DAG.getNOT(dl, N0, OpVT); in SimplifySetCC()
5328 Temp = DAG.getNOT(dl, N1, OpVT); in SimplifySetCC()
5335 Temp = DAG.getNOT(dl, N0, OpVT); in SimplifySetCC()
5342 Temp = DAG.getNOT(dl, N1, OpVT); in SimplifySetCC()
7876 Z = DAG.getNOT(DL, Z, ShVT); in expandFunnelShift()
8796 Op = DAG.getNOT(dl, Op, VT); in expandCTLZ()
8915 ISD::AND, dl, VT, DAG.getNOT(dl, Op, VT), in expandCTTZ()
[all …]
H A DLegalizeVectorOps.cpp1197 SDValue NotMask = DAG.getNOT(DL, Mask, MaskTy); in ExpandSELECT()
1460 SDValue NotMask = DAG.getNOT(DL, Mask, VT); in ExpandVSELECT()
H A DDAGCombiner.cpp6052 SDValue Mask = DAG.getNOT(DL, Diff, OpVT); in foldLogicOfSetCCs()
9347 SDValue NotX = DAG.getNOT(DL, X, VT); in unfoldMaskedMerge()
9349 SDValue NotLHS = DAG.getNOT(DL, LHS, VT); in unfoldMaskedMerge()
9361 SDValue NotY = DAG.getNOT(DL, Y, VT); in unfoldMaskedMerge()
9363 SDValue NotRHS = DAG.getNOT(DL, RHS, VT); in unfoldMaskedMerge()
9368 SDValue NotM = DAG.getNOT(DL, M, VT); in unfoldMaskedMerge()
9527 SDValue NotX = DAG.getNOT(SDLoc(X), X, VT); in visitXOR()
11516 SDValue Not = DAG.getNOT(DL, Sra, VT); in foldVSelectToSignBitSplatMask()
13236 SDValue NotX = DAG.getNOT(DL, X, VT); in foldExtendedSignBitTest()
27088 Shift = DAG.getNOT(DL, Shift, AType); in foldSelectCCToShiftAnd()
[all …]
H A DSelectionDAG.cpp1557 SDValue SelectionDAG::getNOT(const SDLoc &DL, SDValue Val, EVT VT) { in getNOT() function in SelectionDAG
5861 return getNOT(DL, N1, N1.getValueType()); in getNode()
6660 return getNode(ISD::AND, DL, VT, N1, getNOT(DL, N2, VT)); in getNode()
9883 SDValue NotF1 = getNOT(DL, F1, VTList.VTs[0]); in getNode()
H A DLegalizeDAG.cpp3691 Tmp1 = DAG.getNOT(dl, Node->getOperand(1), VT); in ExpandNode()
H A DLegalizeIntegerTypes.cpp4378 SignsMatch = DAG.getNOT(dl, SignsMatch, VT); in ExpandIntRes_SADDSUBO()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsSEISelLowering.cpp1515 DAG.getNOT(DL, Bit, ResTy)); in lowerMSABitClear()
2076 return DAG.getNOT(DL, Res, Res->getValueType(0)); in lowerINTRINSIC_WO_CHAIN()
2082 return DAG.getNOT(DL, Res, Res->getValueType(0)); in lowerINTRINSIC_WO_CHAIN()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/M68k/
H A DM68kISelLowering.cpp2314 Res = DAG.getNOT(DL, Res, Res.getValueType()); in LowerSELECT()
2387 return DAG.getNOT(DL, Res, Res.getValueType()); in LowerSELECT()
/freebsd-14.2/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DSelectionDAG.h1010 SDValue getNOT(const SDLoc &DL, SDValue Val, EVT VT);
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DR600ISelLowering.cpp1085 DstMask = DAG.getNOT(DL, DstMask, MVT::i32); in lowerPrivateTruncStore()
H A DAMDGPUISelLowering.cpp2392 SDValue Not = DAG.getNOT(SL, Shr, MVT::i64); in LowerFTRUNC()
H A DSIISelLowering.cpp6840 DAG.getNOT(SL, BFM, IntVT), BCVec); in lowerINSERT_VECTOR_ELT()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86ISelLowering.cpp22213 V = DAG.getNOT(DL, V, VT); in LowerVectorAllEqual()
22252 V = DAG.getNOT(DL, V, MaskVT); in LowerVectorAllEqual()
23367 Result = DAG.getNOT(dl, Result, VT); in LowerVSETCC()
23450 Result = DAG.getNOT(dl, Result, MVT::v4i32); in LowerVSETCC()
23493 Result = DAG.getNOT(dl, Result, VT); in LowerVSETCC()
24023 Shift = DAG.getNOT(DL, Shift, VT); in LowerSELECT()
44612 Cond = DAG.getNOT(DL, Cond, MVT::i1); in combineSelectOfTwoConstants()
45204 SDValue CondNew = DAG.getNOT(DL, Cond, CondVT); in combineSelect()
47379 return DAG.getNOT(DL, Pack, VT); in combineVectorPack()
52207 return DAG.getNOT(DL, N0, VT); in combineAndnp()
[all …]
H A DX86ISelDAGToDAG.cpp920 Complement = CurDAG->getNOT(dl, Complement, VT); in PreprocessISelDAG()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/LoongArch/
H A DLoongArchISelLowering.cpp2513 DAG.getNOT(DL, Bit, ResTy)); in lowerVectorBitClear()
2803 return DAG.getNOT(DL, Res, Res->getValueType(0)); in performINTRINSIC_WO_CHAINCombine()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyISelLowering.cpp2853 Ret = DAG.getNOT(DL, Ret, MVT::i1); in performSETCCCombine()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMISelLowering.cpp4154 DAG.getSelect(dl, VTy, HiIsZero, Lo, DAG.getNOT(dl, Lo, VTy)); in LowerINTRINSIC_WO_CHAIN()
6808 Merged = DAG.getNOT(dl, Merged, CmpVT); in LowerVSETCC()
6850 Result = DAG.getNOT(dl, Result, VT); in LowerVSETCC()
6862 Result = DAG.getNOT(dl, Result, VT); in LowerVSETCC()
6904 Result = DAG.getNOT(dl, Result, VT); in LowerVSETCC()
6938 Result = DAG.getNOT(dl, Result, VT); in LowerVSETCC()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp9544 Shift = DAG.getNOT(dl, Shift, VT); in LowerSELECT_CC()
13936 return DAG.getNOT(dl, Fcmeq, VT); in EmitVectorComparison()
13980 return DAG.getNOT(dl, Cmeq, VT); in EmitVectorComparison()
14082 Cmp = DAG.getNOT(dl, Cmp, Cmp.getValueType()); in LowerVSETCC()
18211 return DAG.getNOT( in performConcatVectorsCombine()
23602 SDValue InvMask = DAG.getNOT(DL, Mask, VT); in performBSPExpandForSVE()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp11144 return DAG.getNOT(Dl, Rev, MVT::i1); in getDataClassTest()
11163 SDValue Normal(DAG.getNOT( in getDataClassTest()
11171 Sign = DAG.getNOT(Dl, Sign, MVT::i1); in getDataClassTest()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.cpp10268 SDValue Res = DAG.getNOT(DL, OEQ, VT); in lowerVectorStrictFSetcc()
12789 SDValue And = DAG.getNOT(DL, Shl, MVT::i64); in performXORCombine()