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Searched refs:getMinimalPhysRegClass (Results 1 – 25 of 45) sorted by relevance

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/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DRDFCopy.cpp51 if (TRI.getMinimalPhysRegClass(DstR.Reg) != in interpretAsCopy()
52 TRI.getMinimalPhysRegClass(SrcR.Reg)) in interpretAsCopy()
161 const TargetRegisterClass &RC = *TRI.getMinimalPhysRegClass(RR.Reg); in run()
H A DHexagonVLIWPacketizer.cpp714 predRegClass = HRI->getMinimalPhysRegClass(predRegNumSrc); in canPromoteToNewValueStore()
726 predRegClass = HRI->getMinimalPhysRegClass(predRegNumDst); in canPromoteToNewValueStore()
1436 RC = HRI->getMinimalPhysRegClass(DepReg); in isLegalToPacketizeTogether()
H A DHexagonFrameLowering.cpp1421 const TargetRegisterClass *RC = HRI.getMinimalPhysRegClass(Reg); in insertCSRSpillsInBlock()
1485 const TargetRegisterClass *RC = HRI.getMinimalPhysRegClass(Reg); in insertCSRRestoresInBlock()
1668 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(S->Reg); in assignCalleeSavedSpillSlots()
1680 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(R); in assignCalleeSavedSpillSlots()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSILowerSGPRSpills.cpp105 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass( in insertCSRSaves()
146 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass( in insertCSRRestores()
236 TRI->getMinimalPhysRegClass(Reg, MVT::i32); in spillCalleeSavedRegs()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyReplacePhysRegs.cpp83 const TargetRegisterClass *RC = TRI.getMinimalPhysRegClass(PReg); in runOnMachineFunction()
H A DWebAssemblyInstrInfo.cpp67 : MRI.getTargetRegisterInfo()->getMinimalPhysRegClass(DestReg); in copyPhysReg()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsFrameLowering.cpp127 unsigned RegSize = TRI.getSpillSize(*TRI.getMinimalPhysRegClass(*R)); in estimateStackSize()
H A DMipsSEFrameLowering.cpp262 const TargetRegisterClass *DstRC = RegInfo.getMinimalPhysRegClass(Dst); in expandCopyACC()
834 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg); in spillCalleeSavedRegisters()
/freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/
H A DFixupStatepointCallerSaved.cpp93 const TargetRegisterClass *RC = TRI.getMinimalPhysRegClass(Reg); in getRegisterSize()
421 const TargetRegisterClass *RC = TRI.getMinimalPhysRegClass(Reg); in spillRegisters()
431 const TargetRegisterClass *RC = TRI.getMinimalPhysRegClass(Reg); in insertReloadBefore()
H A DRegisterBankInfo.cpp89 const TargetRegisterClass *RC = getMinimalPhysRegClass(Reg, TRI); in getRegBank()
103 RegisterBankInfo::getMinimalPhysRegClass(Register Reg, in getMinimalPhysRegClass() function in RegisterBankInfo
506 auto *RC = getMinimalPhysRegClass(Reg, TRI); in getSizeInBits()
H A DTargetRegisterInfo.cpp213 TargetRegisterInfo::getMinimalPhysRegClass(MCRegister reg, MVT VT) const { in getMinimalPhysRegClass() function in TargetRegisterInfo
510 RC = getMinimalPhysRegClass(Reg); in getRegSizeInBits()
H A DStackMaps.cpp280 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(MOI->getReg()); in parseOperand()
376 unsigned Size = TRI->getSpillSize(*TRI->getMinimalPhysRegClass(Reg)); in createLiveOutReg()
H A DPrologEpilogInserter.cpp496 const TargetRegisterClass *RC = RegInfo->getMinimalPhysRegClass(Reg); in assignCalleeSavedSpillSlots()
626 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg); in insertCSRSaves()
653 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg); in insertCSRRestores()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64LoadStoreOptimizer.cpp917 TRI->getMinimalPhysRegClass(MOP.getReg())); in mergePairedInsns()
937 TRI->getMinimalPhysRegClass(MOP.getReg())); in mergePairedInsns()
1423 auto *RegClass = TRI->getMinimalPhysRegClass(MOP.getReg()); in canRenameMOP()
1519 RequiredClasses.insert(TRI->getMinimalPhysRegClass(MOP.getReg())); in canRenameUpToDef()
1532 RequiredClasses.insert(TRI->getMinimalPhysRegClass(MOP.getReg())); in canRenameUpToDef()
1586 RequiredClasses.insert(TRI->getMinimalPhysRegClass(MOP.getReg())); in canRenameUntilSecondLoad()
1626 auto *RegClass = TRI->getMinimalPhysRegClass(Reg); in tryToFindRegisterToRename()
1654 auto *RegClass = TRI->getMinimalPhysRegClass(getLdStRegOp(FirstMI).getReg()); in findRenameRegForSameLdStRegPair()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AVR/
H A DAVRFrameLowering.cpp271 assert(TRI->getRegSizeInBits(*TRI->getMinimalPhysRegClass(Reg)) == 8 && in spillCalleeSavedRegisters()
308 assert(TRI->getRegSizeInBits(*TRI->getMinimalPhysRegClass(Reg)) == 8 && in restoreCalleeSavedRegisters()
H A DAVRAsmPrinter.cpp127 const TargetRegisterClass *RC = TRI.getMinimalPhysRegClass(Reg); in PrintAsmOperand()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/XCore/
H A DXCoreFrameLowering.cpp437 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg); in spillCalleeSavedRegisters()
463 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg); in restoreCalleeSavedRegisters()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/CSKY/
H A DCSKYFrameLowering.cpp478 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg); in spillCalleeSavedRegisters()
500 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg); in restoreCalleeSavedRegisters()
/freebsd-14.2/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DRegisterBankInfo.h448 getMinimalPhysRegClass(Register Reg, const TargetRegisterInfo &TRI) const;
H A DTargetRegisterInfo.h339 const TargetRegisterClass *getMinimalPhysRegClass(MCRegister Reg,
/freebsd-14.2/contrib/llvm-project/llvm/utils/TableGen/
H A DCodeGenRegisters.h784 getMinimalPhysRegClass(Record *RegRecord, ValueTypeByHwMode *VT = nullptr);
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/LoongArch/
H A DLoongArchFrameLowering.cpp466 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg); in spillCalleeSavedRegisters()
/freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/AsmPrinter/
H A DDwarfExpression.cpp137 const TargetRegisterClass *RC = TRI.getMinimalPhysRegClass(MachineReg); in addMachineReg()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVFrameLowering.cpp1422 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg); in spillCalleeSavedRegisters()
1451 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg); in restoreCalleeSavedRegisters()
/freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DScheduleDAGFast.cpp584 TRI->getMinimalPhysRegClass(Reg, VT); in ListScheduleBottomUp()

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