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Searched refs:getMatchingSuperReg (Results 1 – 25 of 36) sorted by relevance

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/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIMachineFunctionInfo.cpp191 ArgDescriptor::createRegister(TRI.getMatchingSuperReg( in addPrivateSegmentBuffer()
198 ArgInfo.DispatchPtr = ArgDescriptor::createRegister(TRI.getMatchingSuperReg( in addDispatchPtr()
205 ArgInfo.QueuePtr = ArgDescriptor::createRegister(TRI.getMatchingSuperReg( in addQueuePtr()
213 = ArgDescriptor::createRegister(TRI.getMatchingSuperReg( in addKernargSegmentPtr()
220 ArgInfo.DispatchID = ArgDescriptor::createRegister(TRI.getMatchingSuperReg( in addDispatchID()
227 ArgInfo.FlatScratchInit = ArgDescriptor::createRegister(TRI.getMatchingSuperReg( in addFlatScratchInit()
234 ArgInfo.ImplicitBufferPtr = ArgDescriptor::createRegister(TRI.getMatchingSuperReg( in addImplicitBufferPtr()
256 TRI.getMatchingSuperReg(getNextUserSGPR(), AMDGPU::sub0, RC); in addPreloadedKernArg()
H A DR600ControlFlowFinalizer.cpp280 DstMI = TRI->getMatchingSuperReg(Reg, in isCompatibleWithClause()
289 SrcMI = TRI->getMatchingSuperReg(Reg, in isCompatibleWithClause()
H A DSIRegisterInfo.cpp555 return getMatchingSuperReg(BaseReg, AMDGPU::sub0, RC); in getAlignedHighSGPRForRC()
3206 if (MCPhysReg Super = getMatchingSuperReg(Reg, AMDGPU::lo16, &RC)) in get32BitRegister()
3209 if (MCPhysReg Super = getMatchingSuperReg(Reg, AMDGPU::hi16, in get32BitRegister()
/freebsd-14.2/contrib/llvm-project/llvm/lib/MC/
H A DMCRegisterInfo.cpp24 MCRegisterInfo::getMatchingSuperReg(MCRegister Reg, unsigned SubIdx, in getMatchingSuperReg() function in MCRegisterInfo
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/RISCV/Disassembler/
H A DRISCVDisassembler.cpp217 RI->getMatchingSuperReg(RISCV::V0 + RegNo, RISCV::sub_vrm1_0, in DecodeVRM2RegisterClass()
234 RI->getMatchingSuperReg(RISCV::V0 + RegNo, RISCV::sub_vrm1_0, in DecodeVRM4RegisterClass()
251 RI->getMatchingSuperReg(RISCV::V0 + RegNo, RISCV::sub_vrm1_0, in DecodeVRM8RegisterClass()
/freebsd-14.2/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DTargetRegisterInfo.h613 MCRegister getMatchingSuperReg(MCRegister Reg, unsigned SubIdx, in getMatchingSuperReg() function
615 return MCRegisterInfo::getMatchingSuperReg(Reg, SubIdx, RC->MC); in getMatchingSuperReg()
/freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/
H A DCalcSpillWeights.cpp76 return TRI.getMatchingSuperReg(CopiedPReg, Sub, RC); in copyHint()
H A DTwoAddressInstructionPass.cpp1539 assert(TRI->getMatchingSuperReg(RegA, SubRegB, MRI->getRegClass(RegB)) in processTiedPairs()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZShortenInst.cpp89 TRI->getMatchingSuperReg(Reg, thisSubRegIdx, &SystemZ::GR64BitRegClass); in shortenIIF()
H A DSystemZInstrInfo.cpp819 RI.getMatchingSuperReg(RI.getSubReg(SrcReg, SystemZ::subreg_h64), in copyPhysReg()
822 RI.getMatchingSuperReg(RI.getSubReg(SrcReg, SystemZ::subreg_l64), in copyPhysReg()
833 RI.getMatchingSuperReg(RI.getSubReg(DestReg, SystemZ::subreg_h64), in copyPhysReg()
836 RI.getMatchingSuperReg(RI.getSubReg(DestReg, SystemZ::subreg_l64), in copyPhysReg()
H A DSystemZRegisterInfo.cpp116 PhysReg = getMatchingSuperReg(PhysReg, VRRegMO->getSubReg(), in getRegAllocationHints()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMFrameLowering.cpp1791 unsigned SupReg = TRI->getMatchingSuperReg(NextReg, ARM::dsub_0, in emitAlignedDPRCS2Spills()
1810 unsigned SupReg = TRI->getMatchingSuperReg(NextReg, ARM::dsub_0, in emitAlignedDPRCS2Spills()
1825 unsigned SupReg = TRI->getMatchingSuperReg(NextReg, ARM::dsub_0, in emitAlignedDPRCS2Spills()
1923 unsigned SupReg = TRI->getMatchingSuperReg(NextReg, ARM::dsub_0, in emitAlignedDPRCS2Restores()
1941 unsigned SupReg = TRI->getMatchingSuperReg(NextReg, ARM::dsub_0, in emitAlignedDPRCS2Restores()
1954 unsigned SupReg = TRI->getMatchingSuperReg(NextReg, ARM::dsub_0, in emitAlignedDPRCS2Restores()
H A DA15SDOptimizer.cpp145 unsigned DReg = TRI->getMatchingSuperReg(SReg, ARM::ssub_1, in getDPRLaneFromSPR()
H A DARMBaseInstrInfo.cpp1712 unsigned DstRegD = TRI->getMatchingSuperReg(DstRegS, ARM::ssub_0, in expandPostRAPseudo()
1714 unsigned SrcRegD = TRI->getMatchingSuperReg(SrcRegS, ARM::ssub_0, in expandPostRAPseudo()
5076 unsigned DReg = TRI->getMatchingSuperReg(SReg, ARM::ssub_0, &ARM::DPRRegClass); in getCorrespondingDRegAndLane()
5083 DReg = TRI->getMatchingSuperReg(SReg, ARM::ssub_1, &ARM::DPRRegClass); in getCorrespondingDRegAndLane()
5387 unsigned DReg = TRI->getMatchingSuperReg(Reg, ARM::ssub_0, in getPartialRegUpdateClearance()
/freebsd-14.2/contrib/llvm-project/llvm/include/llvm/MC/
H A DMCRegisterInfo.h378 MCRegister getMatchingSuperReg(MCRegister Reg, unsigned SubIdx,
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Sparc/
H A DSparcAsmPrinter.cpp451 MOReg = RegisterInfo->getMatchingSuperReg(MOReg, SP::sub_even, in PrintAsmOperand()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AVR/AsmParser/
H A DAVRAsmParser.cpp84 return MRI->getMatchingSuperReg(Reg, From, Class); in toDREG()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonCopyToCombine.cpp595 unsigned DoubleRegDest = TRI->getMatchingSuperReg(LoRegDef, SubLo, SuperRC); in combine()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/M68k/
H A DM68kInstrInfo.cpp502 Opd.setReg(getRegisterInfo().getMatchingSuperReg( in ExpandCCR()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVAsmPrinter.cpp945 TRI->getMatchingSuperReg(Reg, RISCV::sub_16, &RISCV::FPR32RegClass); in lowerRISCVVMachineInstrToMCInst()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AMDGPU/Disassembler/
H A DAMDGPUDisassembler.cpp1128 NewVdata = MRI.getMatchingSuperReg(Vdata0, AMDGPU::sub0, in convertMIMGInst()
1148 NewVAddrSA = MRI.getMatchingSuperReg(VAddrSA, AMDGPU::sub0, in convertMIMGInst()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AArch64/MCTargetDesc/
H A DAArch64InstPrinter.cpp867 Rm = MRI.getMatchingSuperReg(Rm, AArch64::sub_32, in printRangePrefetchAlias()
1696 Reg = MRI.getMatchingSuperReg(Reg, AArch64::dsub, &FPR128RC); in printVectorList()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64InstrInfo.cpp4404 MCRegister DestRegX = TRI->getMatchingSuperReg( in copyPhysReg()
4406 MCRegister SrcRegX = TRI->getMatchingSuperReg( in copyPhysReg()
4430 MCRegister DestRegX = TRI->getMatchingSuperReg( in copyPhysReg()
4432 MCRegister SrcRegX = TRI->getMatchingSuperReg( in copyPhysReg()
4671 RI.getMatchingSuperReg(DestReg, AArch64::hsub, &AArch64::FPR32RegClass); in copyPhysReg()
4673 RI.getMatchingSuperReg(SrcReg, AArch64::hsub, &AArch64::FPR32RegClass); in copyPhysReg()
4682 RI.getMatchingSuperReg(DestReg, AArch64::bsub, &AArch64::FPR32RegClass); in copyPhysReg()
4684 RI.getMatchingSuperReg(SrcReg, AArch64::bsub, &AArch64::FPR32RegClass); in copyPhysReg()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86InstrInfo.cpp4171 TRI->getMatchingSuperReg(DestReg, X86::sub_xmm, &X86::VR512RegClass); in copyPhysReg()
4173 TRI->getMatchingSuperReg(SrcReg, X86::sub_xmm, &X86::VR512RegClass); in copyPhysReg()
4186 TRI->getMatchingSuperReg(DestReg, X86::sub_ymm, &X86::VR512RegClass); in copyPhysReg()
4188 TRI->getMatchingSuperReg(SrcReg, X86::sub_ymm, &X86::VR512RegClass); in copyPhysReg()
6005 DestReg = TRI->getMatchingSuperReg(DestReg, SubIdx, &X86::VR512RegClass); in expandNOVLXLoad()
6027 SrcReg = TRI->getMatchingSuperReg(SrcReg, SubIdx, &X86::VR512RegClass); in expandNOVLXStore()
6095 TRI->getMatchingSuperReg(SrcReg, X86::sub_xmm, &X86::VR512RegClass); in expandPostRAPseudo()
6114 TRI->getMatchingSuperReg(SrcReg, X86::sub_ymm, &X86::VR512RegClass); in expandPostRAPseudo()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/RISCV/AsmParser/
H A DRISCVAsmParser.cpp1284 return RI.getMatchingSuperReg(Reg, RISCV::sub_vrm1_0, in convertVRToVRMx()
2300 unsigned Pair = RI->getMatchingSuperReg( in parseGPRPair()

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