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Searched refs:getID (Results 1 – 25 of 185) sorted by relevance

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/freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/
H A DRegisterBank.cpp44 assert(RBI.getMaximumSize(getID()) >= TRI.getRegSizeInBits(SubRC) && in verify()
53 return (CoveredClasses[RC.getID() / 32] & (1U << RC.getID() % 32)) != 0; in covers()
60 assert((OtherRB.getID() != getID() || &OtherRB == this) && in operator ==()
81 OS << "(ID:" << getID() << ")\n" in print()
H A DVLIWMachineScheduler.cpp608 << ((Q.getID() == TopQID) ? "(top|" : "(bot|")); in SchedulingCost()
617 if (Q.getID() == TopQID) { in SchedulingCost()
660 if (Q.getID() == TopQID) { in SchedulingCost()
696 if (IsAvailableAmt && pressureChange(SU, Q.getID() != TopQID) > 0 && in SchedulingCost()
709 if (Q.getID() == TopQID && getWeakLeft(SU, true) == 0) { in SchedulingCost()
718 } else if (Q.getID() == BotQID && getWeakLeft(SU, false) == 0) { in SchedulingCost()
735 if (Q.getID() == TopQID) { in SchedulingCost()
803 if ((Q.getID() == TopQID && (*I)->NodeNum < Candidate.SU->NodeNum) || in pickNodeFromQueue()
825 unsigned CurrWeak = getWeakLeft(*I, (Q.getID() == TopQID)); in pickNodeFromQueue()
826 unsigned CandWeak = getWeakLeft(Candidate.SU, (Q.getID() == TopQID)); in pickNodeFromQueue()
[all …]
H A DRegisterBankInfo.cpp64 assert(RegBanks[Idx]->getID() == Idx && in RegisterBankInfo()
74 assert(Idx == RegBank.getID() && in verify()
271 return hash_combine(StartIdx, Length, RegBank ? RegBank->getID() : 0); in hashPartialMapping()
529 assert(RBI.getMaximumSize(RegBank->getID()) >= Length && in verify()
653 OS << "ID: " << getID() << " Cost: " << getCost() << " Mapping: "; in print()
793 OS << "Mapping ID: " << getInstrMapping().getID() << ' '; in print()
/freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DResourcePriorityQueue.cpp329 && TLI->getRegClassFor(VT)->getID() == RCId) in rawRegPressureDelta()
340 && TLI->getRegClassFor(VT)->getID() == RCId) in rawRegPressureDelta()
364 if ((RegPressure[RC->getID()] + in regPressureDelta()
365 rawRegPressureDelta(SU, RC->getID()) > 0) && in regPressureDelta()
366 (RegPressure[RC->getID()] + in regPressureDelta()
367 rawRegPressureDelta(SU, RC->getID()) >= RegLimit[RC->getID()])) in regPressureDelta()
479 RegPressure[RC->getID()] += numberRCValSuccInSU(SU, RC->getID()); in scheduledNode()
490 if (RegPressure[RC->getID()] > in scheduledNode()
491 (numberRCValPredInSU(SU, RC->getID()))) in scheduledNode()
492 RegPressure[RC->getID()] -= numberRCValPredInSU(SU, RC->getID()); in scheduledNode()
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/freebsd-14.2/contrib/llvm-project/clang/lib/Analysis/
H A DIntervalPartition.cpp34 static unsigned getID(const CFGBlock &B) { return B.getBlockID(); } in getID() function
35 static unsigned getID(const CFGIntervalNode &I) { return I.ID; } in getID() function
44 Partitioned.set(getID(*Header)); in buildInterval()
54 if (auto SID = getID(*S); !Partitioned.test(SID)) { in buildInterval()
72 auto ID = getID(*B); in buildInterval()
86 if (auto SID = getID(*S); in buildInterval()
121 assert(getID(*N) < Index.size()); in fillIntervalNode()
122 Index[getID(*N)] = &Interval; in fillIntervalNode()
165 if (Partitioned.test(getID(*B))) in partitionIntoIntervalsImpl()
182 assert(getID(*P) < NumBlockIDs); in partitionIntoIntervalsImpl()
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/freebsd-14.2/contrib/llvm-project/clang/lib/Frontend/
H A DTextDiagnosticPrinter.cpp58 if (Info.getID() == diag::fatal_too_many_errors) { in printDiagnosticOptions()
73 DiagnosticIDs::isBuiltinWarningOrExtension(Info.getID()) && in printDiagnosticOptions()
74 !DiagnosticIDs::isDefaultMappingAsError(Info.getID())) { in printDiagnosticOptions()
79 StringRef Opt = DiagnosticIDs::getWarningOptionForDiag(Info.getID()); in printDiagnosticOptions()
93 DiagnosticIDs::getCategoryNumberForDiag(Info.getID()); in printDiagnosticOptions()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMInstructionSelector.cpp193 assert((RegBank->getID() == ARM::GPRRegBankID || in guessRegClass()
194 RegBank->getID() == ARM::FPRRegBankID) && in guessRegClass()
197 if (RegBank->getID() == ARM::FPRRegBankID) { in guessRegClass()
518 if (RBI.getRegBank(Reg, MRI, TRI)->getID() != ExpectedRegBankID) { in validReg()
922 if (SrcRegBank.getID() == ARM::FPRRegBankID) { in select()
927 assert(DstRegBank.getID() == ARM::GPRRegBankID && in select()
947 if (SrcRegBank.getID() != DstRegBank.getID()) { in select()
953 if (SrcRegBank.getID() != ARM::GPRRegBankID) { in select()
1017 if (SrcRegBank.getID() != DstRegBank.getID()) { in select()
1024 if (SrcRegBank.getID() != ARM::GPRRegBankID) { in select()
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/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonRegisterInfo.cpp92 switch (RC->getID()) { in getCallerSavedRegs()
363 if (!HST.useHVXOps() || NewRC->getID() != Hexagon::HvxWRRegClass.getID()) in shouldCoalesce()
365 bool SmallSrc = SrcRC->getID() == Hexagon::HvxVRRegClass.getID(); in shouldCoalesce()
366 bool SmallDst = DstRC->getID() == Hexagon::HvxVRRegClass.getID(); in shouldCoalesce()
429 switch (RC.getID()) { in getHexagonSubRegIndex()
H A DHexagonMachineScheduler.cpp58 if (Q.getID() == TopQID && in SchedulingCost()
62 } else if (Q.getID() == BotQID && in SchedulingCost()
/freebsd-14.2/contrib/llvm-project/llvm/include/llvm/Option/
H A DOptSpecifier.h29 unsigned getID() const { return ID; } in getID() function
31 bool operator==(OptSpecifier Opt) const { return ID == Opt.getID(); }
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIMachineScheduler.cpp519 unsigned PredID = Pred->getID(); in addPred()
523 if (PredID == P->getID()) in addPred()
531 return PredID == S.first->getID(); in addPred()
538 unsigned SuccID = Succ->getID(); in addSucc()
542 if (SuccID == S.first->getID()) { in addSucc()
1273 if (!--TopDownBlock2Index[Pred->getID()]) in topologicalSort()
1274 WorkList.push_back(Pred->getID()); in topologicalSort()
1463 assert(Block->getID() == i); in SIScheduleBlockScheduler()
1522 dbgs() << ' ' << Block->getID(); in SIScheduleBlockScheduler()
1589 << Block->getID() << ' '; in pickBlock()
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/freebsd-14.2/contrib/llvm-project/llvm/lib/Option/
H A DOption.cpp101 if (getID() == Opt.getID()) in matches()
244 if (getID() == UnaliasedOption.getID()) in accept()
/freebsd-14.2/contrib/llvm-project/clang/lib/Driver/ToolChains/
H A DHLSL.cpp196 if (A->getOption().getID() == options::OPT_dxil_validator_version) { in TranslateArgs()
202 if (A->getOption().getID() == options::OPT_dxc_entrypoint) { in TranslateArgs()
208 if (A->getOption().getID() == options::OPT__SLASH_O) { in TranslateArgs()
220 if (A->getOption().getID() == options::OPT_emit_pristine_llvm) { in TranslateArgs()
/freebsd-14.2/contrib/llvm-project/clang/lib/ARCMigrate/
H A DTransProtectedScope.cpp120 if (I->getID() == diag::err_switch_into_protected_scope && in ProtectedScopeFixer()
133 assert(DiagI->getID() == diag::err_switch_into_protected_scope); in handleProtectedScopeError()
159 Pass.TA.clearDiagnostic(Diag.getID(), Diag.getLocation()); in handleProtectedNote()
/freebsd-14.2/contrib/llvm-project/llvm/include/llvm/Analysis/
H A DMemorySSA.h221 inline unsigned getID() const;
331 OptimizedID = DMA->getID();
339 return getDefiningAccess() && OptimizedID == getDefiningAccess()->getID();
394 OptimizedID = MA->getID();
402 return getOptimized() && OptimizedID == getOptimized()->getID();
412 unsigned getID() const { return ID; }
632 unsigned getID() const { return ID; }
661 inline unsigned MemoryAccess::getID() const {
665 return MD->getID();
666 return cast<MemoryPhi>(this)->getID();
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/
H A DAArch64RegisterBankInfo.cpp75 assert(getMaximumSize(RBGPR.getID()) == 128 && in AArch64RegisterBankInfo()
84 assert(getMaximumSize(RBFPR.getID()) == 512 && in AArch64RegisterBankInfo()
89 assert(getMaximumSize(RBCCR.getID()) == 32 && in AArch64RegisterBankInfo()
242 switch (RC.getID()) { in getRegBankFromRegClass()
404 assert((OpdMapper.getInstrMapping().getID() >= 1 && in applyMappingImpl()
405 OpdMapper.getInstrMapping().getID() <= 4) && in applyMappingImpl()
728 getCopyMapping(DstRB->getID(), SrcRB->getID(), Size), in getInstrMapping()
747 getCopyMapping(DstRB.getID(), SrcRB.getID(), Size), in getInstrMapping()
/freebsd-14.2/contrib/llvm-project/lld/MachO/
H A DDriver.cpp73 switch (outputArg->getOption().getID()) { in getOutputType()
235 switch (arg->getOption().getID()) { in getLTOCachePolicy()
674 assert(arg->getOption().getID() == OPT_platform_version); in parsePlatformVersion()
830 if (arg->getOption().getID() == OPT_objc_stubs_small) { in getObjCStubsMode()
843 if (opt.getGroup().getID() == OPT_grp_deprecated) { in warnIfDeprecatedOption()
852 switch (opt.getGroup().getID()) { in warnIfUnimplementedOption()
1147 switch (opt.getID()) { in createFiles()
1185 opt.getID() == OPT_weak_l, opt.getID() == OPT_reexport_l, in createFiles()
1186 opt.getID() == OPT_hidden_l, in createFiles()
1194 opt.getID() == OPT_weak_framework, in createFiles()
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/freebsd-14.2/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DTargetRegisterInfo.h74 unsigned getID() const { return MC->getID(); } in getID() function
130 unsigned ID = RC->getID(); in hasSubClassEq()
774 return RCInfos[getNumRegClasses() * HwMode + RC.getID()]; in getRegClassInfo()
1308 bool isValid() const { return getID() != NumRegClasses; } in isValid()
1311 unsigned getID() const { return ID; } in getID() function
H A DStackMaps.h47 uint64_t getID() const { return MI->getOperand(IDPos).getImm(); } in getID() function
101 uint64_t getID() const { return getMetaOper(IDPos).getImm(); } in getID() function
204 uint64_t getID() const { return MI->getOperand(NumDefs + IDPos).getImm(); } in getID() function
H A DRegisterBankInfo.h232 unsigned getID() const { return ID; } in getID() function
256 return getID() != InvalidMappingID && OperandsMapping; in isValid()
738 if (OpdMapper.getInstrMapping().getID() == DefaultMappingID) in applyMapping()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/X86/GISel/
H A DX86InstructionSelector.cpp175 if (RB.getID() == X86::GPRRegBankID) { in getRegClass()
185 if (RB.getID() == X86::VECRRegBankID) { in getRegClass()
454 if (X86::GPRRegBankID == RB.getID()) in getLoadStoreOp()
457 if (X86::GPRRegBankID == RB.getID()) in getLoadStoreOp()
460 if (X86::GPRRegBankID == RB.getID()) in getLoadStoreOp()
462 if (X86::VECRRegBankID == RB.getID()) in getLoadStoreOp()
470 if (X86::GPRRegBankID == RB.getID()) in getLoadStoreOp()
472 if (X86::VECRRegBankID == RB.getID()) in getLoadStoreOp()
771 if (DstRB.getID() != SrcRB.getID()) { in selectTruncOrPtrToInt()
789 if (DstRB.getID() != X86::GPRRegBankID) in selectTruncOrPtrToInt()
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/freebsd-14.2/contrib/llvm-project/llvm/lib/DebugInfo/LogicalView/Core/
H A DLVReader.cpp71 return std::get<0>(l)->getID() < std::get<0>(r)->getID(); in checkIntegrityScopesTree()
84 Element->getID(), ElementName.c_str()); in checkIntegrityScopesTree()
/freebsd-14.2/contrib/llvm-project/llvm/utils/TableGen/
H A DDAGISelEmitter.cpp120 return LHS->getID() < RHS->getID(); in operator ()()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/PowerPC/GISel/
H A DPPCRegisterBankInfo.cpp35 switch (RC.getID()) { in getRegBankFromRegClass()
232 MappingID, Cost, getCopyMapping(DstRB.getID(), SrcRB.getID(), DstSize), in getInstrMapping()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/SPIRV/
H A DSPIRVInstrInfo.cpp53 return DefRegClass && DefRegClass->getID() == SPIRV::TYPERegClass.getID(); in isTypeDeclInstr()

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