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Searched refs:getFixedSizeInBits (Results 1 – 25 of 29) sorted by relevance

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/freebsd-14.2/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DMachineValueType.h138 return (isFixedLengthVector() && getFixedSizeInBits() == 16); in is16BitVector()
143 return (isFixedLengthVector() && getFixedSizeInBits() == 32); in is32BitVector()
148 return (isFixedLengthVector() && getFixedSizeInBits() == 64); in is64BitVector()
153 return (isFixedLengthVector() && getFixedSizeInBits() == 128); in is128BitVector()
158 return (isFixedLengthVector() && getFixedSizeInBits() == 256); in is256BitVector()
163 return (isFixedLengthVector() && getFixedSizeInBits() == 512); in is512BitVector()
168 return (isFixedLengthVector() && getFixedSizeInBits() == 1024); in is1024BitVector()
173 return (isFixedLengthVector() && getFixedSizeInBits() == 2048); in is2048BitVector()
338 uint64_t getFixedSizeInBits() const { in getFixedSizeInBits() function
H A DValueTypes.h359 uint64_t getFixedSizeInBits() const { in getFixedSizeInBits() function
H A DSelectionDAGNodes.h204 return getValueType().getScalarType().getFixedSizeInBits();
/freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/
H A DTypePromotion.cpp940 if (RegisterBitWidth < PromotedVT.getFixedSizeInBits()) { in run()
947 return PromotedVT.getFixedSizeInBits(); in run()
968 auto PromoteWidth = ZExtVT.getFixedSizeInBits(); in run()
H A DTargetLoweringBase.cpp808 MVT IntVT = MVT::getIntegerVT(VT.getFixedSizeInBits()); in initActions()
1480 if (SVT.getScalarSizeInBits() > EltVT.getFixedSizeInBits() && in computeRegisterProperties()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMCallLowering.cpp290 uint64_t ValSize = VA.getValVT().getFixedSizeInBits(); in assignValueToReg()
291 uint64_t LocSize = VA.getLocVT().getFixedSizeInBits(); in assignValueToReg()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64Subtarget.h426 return VT.getFixedSizeInBits() > AArch64::SVEBitsPerBlock || in useSVEForFixedLengthVectors()
H A DAArch64ISelLowering.cpp4043 uint64_t VTSize = VT.getFixedSizeInBits(); in LowerVectorFP_TO_INT()
4044 uint64_t InVTSize = InVT.getFixedSizeInBits(); in LowerVectorFP_TO_INT()
4280 uint64_t VTSize = VT.getFixedSizeInBits(); in LowerVectorINT_TO_FP()
4281 uint64_t InVTSize = InVT.getFixedSizeInBits(); in LowerVectorINT_TO_FP()
6463 if (VT.getFixedSizeInBits() <= 128) in useSVEForFixedLengthVectorVT()
10651 if (VT.getFixedSizeInBits() == 64) in getRegForInlineAsmConstraint()
11165 uint64_t VTSize = VT.getFixedSizeInBits(); in ReconstructShuffle()
11257 SrcEltTy.getFixedSizeInBits() / SmallestEltTy.getFixedSizeInBits(); in ReconstructShuffle()
14722 uint64_t NumBits1 = VT1.getFixedSizeInBits(); in isTruncateFree()
14723 uint64_t NumBits2 = VT2.getFixedSizeInBits(); in isTruncateFree()
[all …]
H A DAArch64TargetTransformInfo.cpp2664 if (DstVT.getFixedSizeInBits() < SrcVT.getFixedSizeInBits()) in getExtractWithExtendCost()
H A DAArch64ISelDAGToDAG.cpp287 /* High */ EltVT.getFixedSizeInBits(), in SelectSVEShiftSplatImmR()
3980 .trunc(VT.getFixedSizeInBits()) in SelectSVEAddSubImm()
4020 .trunc(VT.getFixedSizeInBits()) in SelectSVECpyDupImm()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/MSP430/
H A DMSP430ISelLowering.cpp1398 return (VT1.getFixedSizeInBits() > VT2.getFixedSizeInBits()); in isTruncateFree()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyISelLowering.cpp2188 size_t DestLaneSize = VecT.getVectorElementType().getFixedSizeInBits() / 8; in LowerBUILD_VECTOR()
2196 Src1.getValueType().getVectorElementType().getFixedSizeInBits() / 8; in LowerBUILD_VECTOR()
2203 Src2.getValueType().getVectorElementType().getFixedSizeInBits() / 8; in LowerBUILD_VECTOR()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/NVPTX/
H A DNVPTXISelLowering.cpp251 switch (PowerOf2Ceil(VT.getFixedSizeInBits())) { in PromoteScalarIntegerPTX()
3182 Ins[InsIdx].VT.getFixedSizeInBits() > in LowerFormalArguments()
3183 LoadVT.getFixedSizeInBits()) { in LowerFormalArguments()
5367 if (OrigVT.getFixedSizeInBits() <= OptSize) { in IsMulWideOperandDemotable()
5373 if (OrigVT.getFixedSizeInBits() <= OptSize) { in IsMulWideOperandDemotable()
/freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeVectorTypes.cpp1823 EltVT.getFixedSizeInBits() / 8)); in SplitVecRes_INSERT_VECTOR_ELT()
3413 commonAlignment(SmallestAlign, EltVT.getFixedSizeInBits() / 8)); in SplitVecOp_EXTRACT_VECTOR_ELT()
6357 unsigned EltSize = EltVT.getFixedSizeInBits(); in WidenVecOp_BITCAST()
6437 SubVT.getFixedSizeInBits()) in WidenVecOp_INSERT_SUBVECTOR()
6954 if (RetVT.getFixedSizeInBits() < MemVTWidth || MemVT == WidenVT) in findMemType()
7246 unsigned ValEltWidth = ValEltVT.getFixedSizeInBits(); in GenWidenVectorStores()
H A DTargetLowering.cpp9705 unsigned NumBits = NewStoredVT.getFixedSizeInBits(); in expandUnalignedStore()
9771 APInt(AddrVT.getFixedSizeInBits(), in IncrementMemoryAddress()
9797 DAG.getVScale(dl, IdxVT, APInt(IdxVT.getFixedSizeInBits(), NElts)); in clampDynamicVectorIndex()
9833 unsigned EltSize = EltVT.getFixedSizeInBits() / 8; // FIXME: should be ABI size. in getVectorSubVecPointer()
9834 assert(EltSize * 8 == EltVT.getFixedSizeInBits() && in getVectorSubVecPointer()
10545 unsigned LoSize = VT.getFixedSizeInBits(); in expandMULO()
10850 APInt(PtrVT.getFixedSizeInBits(), VT.getStoreSize().getKnownMinValue())); in expandVectorSplice()
10873 APInt(PtrVT.getFixedSizeInBits(), in expandVectorSplice()
H A DSelectionDAGBuilder.cpp458 const uint64_t ValueSize = ValueVT.getFixedSizeInBits(); in getCopyFromPartsVector()
732 uint64_t ValueSize = ValueVT.getFixedSizeInBits(); in getCopyToPartsVector()
733 assert(PartVT.getFixedSizeInBits() > ValueSize && in getCopyToPartsVector()
6939 if (PtrTy.getFixedSizeInBits() < ResTy.getFixedSizeInBits()) in visitIntrinsicCall()
H A DDAGCombiner.cpp7341 LHS.getOperand(0).getValueType().getFixedSizeInBits())) in visitAND()
18666 DAG.getConstant(APInt::getLowBitsSet(STType.getFixedSizeInBits(), in ForwardStoreValueToDirectLoad()
21232 if (STBase.contains(DAG, ST->getMemoryVT().getFixedSizeInBits(), in visitSTORE()
21234 ST1->getMemoryVT().getFixedSizeInBits())) { in visitSTORE()
22740 uint64_t VTSize = VT.getFixedSizeInBits(); in createBuildVecShuffle()
22741 uint64_t InVT1Size = InVT1.getFixedSizeInBits(); in createBuildVecShuffle()
22742 uint64_t InVT2Size = InVT2.getFixedSizeInBits(); in createBuildVecShuffle()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Sparc/
H A DSparcISelLowering.cpp2775 Align(std::min(PtrVT.getFixedSizeInBits(), VT.getFixedSizeInBits()) / 8)); in LowerVAARG()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.cpp2449 if (VT.getFixedSizeInBits() > 1024 * 8) in useRVVForFixedLengthVectorVT()
3814 unsigned ElemsPerVReg = MinVLen / ElemVT.getFixedSizeInBits(); in lowerBUILD_VECTOR()
4678 unsigned ElemsPerVReg = MinVLen / ElemVT.getFixedSizeInBits(); in lowerShuffleViaVRegSplitting()
6832 LLT(Ty.getSimpleVT()), Align(Ty.getFixedSizeInBits() / 8)); in getAddr()
6862 LLT(Ty.getSimpleVT()), Align(Ty.getFixedSizeInBits() / 8)); in getAddr()
6925 LLT(Ty.getSimpleVT()), Align(Ty.getFixedSizeInBits() / 8)); in getStaticTLSAddr()
7952 unsigned ElemsPerVReg = MinVLen / ElemVT.getFixedSizeInBits(); in lowerINSERT_VECTOR_ELT()
8165 unsigned ElemsPerVReg = MinVLen / ElemVT.getFixedSizeInBits(); in lowerEXTRACT_VECTOR_ELT()
19876 unsigned Count = PartVTBitSize / ValueEltVT.getFixedSizeInBits(); in splitValueIntoRegisterParts()
19929 unsigned Count = PartVTBitSize / ValueEltVT.getFixedSizeInBits(); in joinRegisterPartsIntoValue()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp6800 if (ValVT.getFixedSizeInBits() < RegVT.getFixedSizeInBits()) in CC_AIX()
6989 assert(ValVT.getFixedSizeInBits() < LocVT.getFixedSizeInBits()); in truncateScalarIntegerArg()
7295 (ValVT.getFixedSizeInBits() < LocVT.getFixedSizeInBits())) { in LowerFormalArguments_AIX()
7616 else if (Arg.getValueType().getFixedSizeInBits() < in LowerCall_AIX()
7617 LocVT.getFixedSizeInBits()) in LowerCall_AIX()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUISelLowering.cpp3087 auto const LeadingZeroes = 32u - ResultVT.getFixedSizeInBits(); in lowerCTLZResults()
4102 if (VT.getFixedSizeInBits() <= EltVT.getFixedSizeInBits()) { in performTruncateCombine()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86ISelLoweringCall.cpp2689 if (VA.getLocVT().getFixedSizeInBits() > in MatchingStackOffset()
H A DX86ISelLowering.cpp3877 assert(Vec.getValueSizeInBits().getFixedValue() <= VT.getFixedSizeInBits() && in widenSubVector()
5820 return SubVT.getFixedSizeInBits() < in getFauxShuffleMask()
23192 if (VT.getFixedSizeInBits() > in LowerVSETCC()
23193 Op.getSimpleValueType().getFixedSizeInBits()) { in LowerVSETCC()
24223 assert(SVT.getFixedSizeInBits() > InSVT.getFixedSizeInBits()); in LowerEXTEND_VECTOR_INREG()
39948 VT.getFixedSizeInBits()) { in combineTargetShuffle()
49819 if (InScalarVT.getFixedSizeInBits() <= ScalarVT.getFixedSizeInBits()) in detectAVGPattern()
50028 RegVT.getFixedSizeInBits()) { in combineLoad()
55309 SubVecVT.getFixedSizeInBits()) in combineINSERT_SUBVECTOR()
55731 unsigned SizeInBits = VT.getFixedSizeInBits(); in combineScalarToVector()
[all …]
/freebsd-14.2/contrib/llvm-project/llvm/utils/TableGen/
H A DCodeGenDAGPatterns.cpp2492 unsigned Size = MVT(VT).getFixedSizeInBits(); in ApplyTypeConstraints()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonISelLoweringHVX.cpp412 int ElemWidth = ElemTy.getFixedSizeInBits(); in initializeHVXLowering()

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