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Searched refs:fp32 (Results 1 – 10 of 10) sorted by relevance

/freebsd-14.2/sys/net/
H A Dbpf.c1951 struct bpf_program32 *fp32; in bpf_setf() local
1967 fp32 = (struct bpf_program32 *)fp; in bpf_setf()
1968 fp_swab.bf_len = fp32->bf_len; in bpf_setf()
1970 (struct bpf_insn *)(uintptr_t)fp32->bf_insns; in bpf_setf()
/freebsd-14.2/contrib/llvm-project/clang/include/clang/Basic/
H A DCodeGenOptions.def185 CODEGENOPT(OpenCLCorrectlyRoundedDivSqrt, 1, 0) ///< -cl-fp32-correctly-rounded-divide-sqrt
186 CODEGENOPT(HIPCorrectlyRoundedDivSqrt, 1, 1) ///< -fno-hip-fp32-correctly-rounded-divide-sqrt
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPU.td493 def FeaturePackedFP32Ops : SubtargetFeature<"packed-fp32-ops",
496 "Support packed fp32 instructions"
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZInstrFP.td323 // be used with fp32 as well. This could be done for fp128, in which
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonPatternsHVX.td448 // For now we assume that the fp32 register is always coming in as IEEE float
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/NVPTX/
H A DNVPTXInstrInfo.td266 // Template for instructions which take three fp64 or fp32 args. The
270 // zero) variants for fp32 functions.
365 // zero) variants for fp32/fp16 functions.
H A DNVPTXIntrinsics.td6416 // fp16 -> fp16/fp32 @ m16n16k16
6424 // fp16 -> fp16/fp32 @ m8n32k16/m32n8k16
/freebsd-14.2/contrib/llvm-project/clang/lib/Sema/
H A DOpenCLBuiltins.td482 // GenType definitions for every single base type (e.g. fp32 only).
/freebsd-14.2/contrib/llvm-project/llvm/include/llvm/IR/
H A DIntrinsicsNVVM.td70 // wmma fp16 -> fp16/fp32 @ m16n16k16/m8n32k16/m32n8k16
/freebsd-14.2/contrib/llvm-project/clang/include/clang/Driver/
H A DOptions.td1081 def cl_fp32_correctly_rounded_divide_sqrt : Flag<["-"], "cl-fp32-correctly-rounded-divide-sqrt">, G…
1348 defm hip_fp32_correctly_rounded_divide_sqrt : BoolFOption<"hip-fp32-correctly-rounded-divide-sqrt",