| /freebsd-14.2/contrib/llvm-project/compiler-rt/lib/builtins/loongarch/ |
| H A D | fp_mode.c | 22 int fcsr; in __fe_getround() local
24 __asm__ __volatile__("movfcsr2gr %0, $fcsr0" : "=r" (fcsr)); in __fe_getround()
26 __asm__ __volatile__("movfcsr2gr %0, $r0" : "=r" (fcsr)); in __fe_getround()
28 fcsr &= LOONGARCH_RMODE_MASK; in __fe_getround()
29 switch (fcsr) { in __fe_getround()
47 int fcsr; in __fe_raise_inexact() local
49 __asm__ __volatile__("movfcsr2gr %0, $fcsr0" : "=r" (fcsr)); in __fe_raise_inexact()
51 "movgr2fcsr $fcsr0, %0" :: "r" (fcsr | LOONGARCH_INEXACT)); in __fe_raise_inexact()
53 __asm__ __volatile__("movfcsr2gr %0, $r0" : "=r" (fcsr)); in __fe_raise_inexact()
55 "movgr2fcsr $r0, %0" :: "r" (fcsr | LOONGARCH_INEXACT)); in __fe_raise_inexact()
|
| /freebsd-14.2/contrib/llvm-project/lldb/source/Plugins/Instruction/MIPS64/ |
| H A D | EmulateInstructionMIPS64.cpp | 1984 uint32_t cc, fcsr; in Emulate_FP_branch() local
2002 fcsr = in Emulate_FP_branch()
2008 fcsr = ((fcsr >> 24) & 0xfe) | ((fcsr >> 23) & 0x01); in Emulate_FP_branch()
2012 if ((fcsr & (1 << cc)) == 0) in Emulate_FP_branch()
2018 if ((fcsr & (1 << cc)) != 0) in Emulate_FP_branch()
2111 uint32_t cc, fcsr; in Emulate_3D_branch() local
2128 fcsr = ((fcsr >> 24) & 0xfe) | ((fcsr >> 23) & 0x01); in Emulate_3D_branch()
2132 if (((fcsr >> cc) & 3) != 3) in Emulate_3D_branch()
2138 if (((fcsr >> cc) & 3) != 0) in Emulate_3D_branch()
2144 if (((fcsr >> cc) & 0xf) != 0xf) in Emulate_3D_branch()
[all …]
|
| /freebsd-14.2/contrib/llvm-project/lldb/source/Plugins/Instruction/MIPS/ |
| H A D | EmulateInstructionMIPS.cpp | 2671 uint32_t cc, fcsr; in Emulate_FP_branch() local
2687 fcsr = ((fcsr >> 24) & 0xfe) | ((fcsr >> 23) & 0x01); in Emulate_FP_branch()
2691 if ((fcsr & (1 << cc)) == 0) in Emulate_FP_branch()
2697 if ((fcsr & (1 << cc)) != 0) in Emulate_FP_branch()
2789 uint32_t cc, fcsr; in Emulate_3D_branch() local
2800 fcsr = (uint32_t)ReadRegisterUnsigned(eRegisterKindDWARF, dwarf_fcsr_mips, 0, in Emulate_3D_branch()
2806 fcsr = ((fcsr >> 24) & 0xfe) | ((fcsr >> 23) & 0x01); in Emulate_3D_branch()
2810 if (((fcsr >> cc) & 3) != 3) in Emulate_3D_branch()
2816 if (((fcsr >> cc) & 3) != 0) in Emulate_3D_branch()
2822 if (((fcsr >> cc) & 0xf) != 0xf) in Emulate_3D_branch()
[all …]
|
| /freebsd-14.2/contrib/llvm-project/lldb/source/Plugins/Process/Utility/ |
| H A D | RegisterInfoPOSIX_riscv64.h | 35 uint32_t fcsr; member
|
| H A D | RegisterInfoPOSIX_loongarch64.h | 43 uint32_t fcsr; member
|
| H A D | RegisterContext_mips.h | 319 uint32_t fcsr; member
361 uint32_t fcsr; /* FPU control status register */ member
|
| H A D | RegisterContextFreeBSD_mips64.cpp | 141 uint64_t fcsr; member
|
| H A D | RegisterInfos_mips.h | 211 DEFINE_FPR_INFO(fcsr, nullptr, dwarf_fcsr_mips, dwarf_fcsr_mips,
285 DEFINE_MSA_INFO(fcsr, nullptr, dwarf_fcsr_mips, dwarf_fcsr_mips,
|
| H A D | RegisterInfos_loongarch64.h | 168 DEFINE_FCSR(fcsr, LLDB_INVALID_REGNUM),
|
| H A D | RegisterInfos_riscv64.h | 150 DEFINE_FPR_ALT(fcsr, nullptr, 4, LLDB_INVALID_REGNUM),
|
| H A D | RegisterInfos_mips64.h | 203 DEFINE_FPR_INFO(fcsr, nullptr, dwarf_fcsr_mips64, dwarf_fcsr_mips64,
|
| /freebsd-14.2/crypto/openssl/crypto/poly1305/ |
| H A D | poly1305_ieee754.c | 105 static const u32 fcsr = 1; variable
156 asm volatile ("ctc1 %0,$31"::"r"(fcsr)); in poly1305_init()
278 asm volatile ("ctc1 %0,$31"::"r"(fcsr)); in poly1305_blocks()
|
| /freebsd-14.2/contrib/llvm-project/lldb/source/Plugins/Instruction/RISCV/ |
| H A D | EmulateInstructionRISCV.cpp | 1654 auto fcsr = ReadRegisterUnsigned(eRegisterKindLLDB, fpr_fcsr_riscv, in GetRoundingMode() local
1658 auto frm = (fcsr >> 5) & 0x7; in GetRoundingMode()
1679 auto fcsr = ReadRegisterUnsigned(eRegisterKindLLDB, fpr_fcsr_riscv, in SetAccruedExceptions() local
1685 fcsr |= 1 << 4; in SetAccruedExceptions()
1688 fcsr |= 1 << 3; in SetAccruedExceptions()
1691 fcsr |= 1 << 2; in SetAccruedExceptions()
1694 fcsr |= 1 << 1; in SetAccruedExceptions()
1697 fcsr |= 1 << 0; in SetAccruedExceptions()
1705 return WriteRegisterUnsigned(ctx, eRegisterKindLLDB, fpr_fcsr_riscv, fcsr); in SetAccruedExceptions()
|
| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/LoongArch/ |
| H A D | LoongArchRegisterInfo.td | 185 def FCSR#I : LoongArchReg<I, "fcsr"#I>;
|
| H A D | LoongArchInstrInfo.td | 2194 def WRFCSR : Pseudo<(outs), (ins uimm2:$fcsr, GPR:$src),
2195 [(loongarch_movgr2fcsr uimm2:$fcsr, GRLenVT:$src)]>;
2196 def RDFCSR : Pseudo<(outs GPR:$rd), (ins uimm2:$fcsr),
2197 [(set GPR:$rd, (loongarch_movfcsr2gr uimm2:$fcsr))]>;
|
| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVSystemOperands.td | 79 def SysRegFCSR : SysReg<"fcsr", 0x003>;
|
| /freebsd-14.2/sys/riscv/include/ |
| H A D | encoding.h | 1026 DECLARE_CSR(fcsr, CSR_FCSR)
|