Home
last modified time | relevance | path

Searched refs:f64 (Results 1 – 25 of 215) sorted by relevance

123456789

/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyInstrFloat.td23 !strconcat("f64.", name), f64Inst>;
34 !strconcat("f64.", name), f64Inst>;
77 def : Pat<(frint f64:$src), (NEAREST_F64 f64:$src)>;
81 def : Pat<(froundeven f64:$src), (NEAREST_F64 f64:$src)>;
99 def : Pat<(seteq f64:$lhs, f64:$rhs), (EQ_F64 f64:$lhs, f64:$rhs)>;
100 def : Pat<(setne f64:$lhs, f64:$rhs), (NE_F64 f64:$lhs, f64:$rhs)>;
101 def : Pat<(setlt f64:$lhs, f64:$rhs), (LT_F64 f64:$lhs, f64:$rhs)>;
102 def : Pat<(setle f64:$lhs, f64:$rhs), (LE_F64 f64:$lhs, f64:$rhs)>;
103 def : Pat<(setgt f64:$lhs, f64:$rhs), (GT_F64 f64:$lhs, f64:$rhs)>;
104 def : Pat<(setge f64:$lhs, f64:$rhs), (GE_F64 f64:$lhs, f64:$rhs)>;
[all …]
H A DWebAssemblyInstrConv.td193 "f64.convert_i32_s\t$dst, $src", "f64.convert_i32_s",
197 "f64.convert_i32_u\t$dst, $src", "f64.convert_i32_u",
209 "f64.convert_i64_s\t$dst, $src", "f64.convert_i64_s",
213 "f64.convert_i64_u\t$dst, $src", "f64.convert_i64_u",
218 "f64.promote_f32\t$dst, $src", "f64.promote_f32",
239 "f64.reinterpret_i64\t$dst, $src",
240 "f64.reinterpret_i64", 0xbf>;
/freebsd-14.2/lib/libc/arm/aeabi/
H A Daeabi_vfp_double.S38 vcmp.f64 d0, d1
47 vcmpe.f64 d0, d1
56 vcmpe.f64 d1, d0
65 vcmp.f64 d0, d1
77 vcmp.f64 d0, d1
89 vcmp.f64 d0, d1
101 vcmp.f64 d0, d1
113 vcmp.f64 d0, d1
125 vcmp.f64 d0, d1
142 vcvt.s32.f64 s0, d0
[all …]
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCInstrVSX.td404 [(set f64:$XT, (any_fma f64:$XA, f64:$XB, f64:$XTi))]>,
420 [(set f64:$XT, (any_fma f64:$XA, f64:$XB, (fneg f64:$XTi)))]>,
436 [(set f64:$XT, (fneg (any_fma f64:$XA, f64:$XB, f64:$XTi)))]>,
452 [(set f64:$XT, (fneg (any_fma f64:$XA, f64:$XB, (fneg f64:$XTi))))]>,
2515 def : Pat<(PPCfnmsub f64:$A, f64:$B, f64:$C),
2517 def : Pat<(fneg (PPCfnmsub f64:$A, f64:$B, f64:$C)),
2519 def : Pat<(PPCfnmsub f64:$A, f64:$B, (fneg f64:$C)),
2755 def : Pat<(f64 (fminnum_ieee f64:$A, f64:$B)),
2757 def : Pat<(f64 (fminnum_ieee (fcanonicalize f64:$A), f64:$B)),
2764 def : Pat<(f64 (fmaxnum_ieee f64:$A, f64:$B)),
[all …]
H A DPPCInstrSPE.td142 [(set f64:$RT, (any_fadd f64:$RA, f64:$RB))]>;
211 [(set f64:$RT, (any_fdiv f64:$RA, f64:$RB))]>;
215 [(set f64:$RT, (any_fmul f64:$RA, f64:$RB))]>;
227 [(set f64:$RT, (any_fsub f64:$RA, f64:$RB))]>;
851 def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETLT)),
853 def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETULT)),
855 def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETLE)),
859 def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETEQ)),
861 def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETGE)),
865 def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETGT)),
[all …]
H A DREADME_P9.txt202 [(set f64:$XT, (PPCfrsqrte f64:$XB))]>;
314 (set i128:$XT, (int_ppc_vsx_xscmpeqdp f64:$XA, f64:$XB))
315 (set i128:$XT, (int_ppc_vsx_xscmpgedp f64:$XA, f64:$XB))
316 (set i128:$XT, (int_ppc_vsx_xscmpgtdp f64:$XA, f64:$XB))
317 (set i128:$XT, (int_ppc_vsx_xscmpnedp f64:$XA, f64:$XB))
467 (set f64:$XT, (fmaxnum f64:$XA, f64:$XB))
468 (set f64:$XT, (fminnum f64:$XA, f64:$XB))
471 (set f64:$XT, (int_ppc_vsx_xsmaxjdp f64:$XA, f64:$XB))
472 (set f64:$XT, (int_ppc_vsx_xsminjdp f64:$XA, f64:$XB))
515 . (set f64:$XT, (load iaddrX4:$src))
[all …]
/freebsd-14.2/contrib/llvm-project/llvm/include/llvm/Analysis/
H A DVecFuncs.def74 TLI_DEFINE_VECFUNC("llvm.exp.f64", "_simd_exp_d2", FIXED(2), "_ZGV_LLVM_N2v")
90 TLI_DEFINE_VECFUNC("llvm.cos.f64", "_simd_cos_d2", FIXED(2), "_ZGV_LLVM_N2v")
95 TLI_DEFINE_VECFUNC("llvm.sin.f64", "_simd_sin_d2", FIXED(2), "_ZGV_LLVM_N2v")
132 TLI_DEFINE_VECFUNC("llvm.sin.f64", "_ZGVbN2v_sin", FIXED(2), "_ZGV_LLVM_N2v")
211 TLI_DEFINE_VECFUNC("llvm.pow.f64", "__powd2", FIXED(2), "_ZGV_LLVM_N2vv")
217 TLI_DEFINE_VECFUNC("llvm.exp.f64", "__expd2", FIXED(2), "_ZGV_LLVM_N2v")
221 TLI_DEFINE_VECFUNC("llvm.exp2.f64", "__exp2d2", FIXED(2), "_ZGV_LLVM_N2v")
227 TLI_DEFINE_VECFUNC("llvm.log.f64", "__logd2", FIXED(2), "_ZGV_LLVM_N2v")
237 TLI_DEFINE_VECFUNC("llvm.log2.f64", "__log2d2", FIXED(2), "_ZGV_LLVM_N2v")
243 TLI_DEFINE_VECFUNC("llvm.sin.f64", "__sind2", FIXED(2), "_ZGV_LLVM_N2v")
[all …]
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMCallingConv.td32 // Handle all vector types as either f64 or v2f64.
43 CCIfType<[f64], CCAssignToStack<8, 4>>,
58 // Handle all vector types as either f64 or v2f64.
73 // Handle all vector types as either f64 or v2f64.
93 // Handle all vector types as either f64 or v2f64.
110 // Handle all vector types as either f64 or v2f64.
115 CCIfType<[f64], CCAssignToReg<[D8, D9, D10, D11]>>,
133 // i64/f64 is passed in even pairs of GPRs
167 // Handle all vector types as either f64 or v2f64.
185 // Handle all vector types as either f64 or v2f64.
[all …]
H A DARMInstrVFP.td99 def vfp_f64imm : Operand<f64>,
100 PatLeaf<(f64 fpimm), [{
542 [(set DPR:$Dd, (ARMcmov (f64 DPR:$Dm), (f64 DPR:$Dn), CC))]>,
571 [(set DPR:$Dd, (f64 (SD (f64 DPR:$Dn), (f64 DPR:$Dm))))]>,
838 def : FP16Pat<(f64 (f16_to_fp GPR:$a)),
863 def : FP16Pat<(fp_to_f16 (f64 DPR:$a)),
1042 [(set (f64 DPR:$Dd), (node (f64 DPR:$Dm)))]>,
1054 def : InstAlias<!strconcat("vrint", opc, "$p.f64.f64\t$Dd, $Dm"),
1084 [(set (f64 DPR:$Dd), (node (f64 DPR:$Dm)))]>,
1096 def : InstAlias<!strconcat("vrint", opc, ".f64.f64\t$Dd, $Dm"),
[all …]
H A DARMInstrCDE.td552 def : Pat<(f64 (int_arm_cde_vcx1 timm:$coproc, timm:$imm)),
553 (f64 (CDE_VCX1_fpdp p_imm:$coproc, imm_11b:$imm))>;
554 def : Pat<(f64 (int_arm_cde_vcx1a timm:$coproc, (f64 DPR:$acc), timm:$imm)),
555 (f64 (CDE_VCX1A_fpdp p_imm:$coproc, DPR:$acc, imm_11b:$imm))>;
562 def : Pat<(f64 (int_arm_cde_vcx2 timm:$coproc, (f64 DPR:$n), timm:$imm)),
563 (f64 (CDE_VCX2_fpdp p_imm:$coproc, DPR:$n, imm_6b:$imm))>;
564 def : Pat<(f64 (int_arm_cde_vcx2a timm:$coproc, (f64 DPR:$acc), (f64 DPR:$n),
576 def : Pat<(f64 (int_arm_cde_vcx3 timm:$coproc, (f64 DPR:$n), (f64 DPR:$m),
579 def : Pat<(f64 (int_arm_cde_vcx3a timm:$coproc, (f64 DPR:$acc), (f64 DPR:$n),
580 (f64 DPR:$m), timm:$imm)),
[all …]
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsCallingConv.td57 CCBitConvertToType<f64>,
90 CCIfType<[f64], CCAssignToStack<8, 8>>
157 // f64 arguments are passed in double precision FP registers.
165 CCIfType<[i64, f64], CCAssignToStack<8, 8>>
185 CCIfType<[i64, f64], CCAssignToStack<8, 8>>
216 // f64 are returned in registers D0, D2
217 CCIfType<[f64], CCAssignToReg<[D0_64, D2_64]>>
225 CCIfType<[f64], CCIfSubtargetNot<"isFP64bit()",
241 CCIfType<[f64], CCAssignToStack<8, 8>>
258 CCIfType<[i64, f64], CCAssignToStack<8, 8>>
[all …]
/freebsd-14.2/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DValueTypes.td199 def v1f64 : VTVec<1, f64, 125>; // 1 x f64 vector value
200 def v2f64 : VTVec<2, f64, 126>; // 2 x f64 vector value
201 def v3f64 : VTVec<3, f64, 127>; // 3 x f64 vector value
202 def v4f64 : VTVec<4, f64, 128>; // 4 x f64 vector value
203 def v8f64 : VTVec<8, f64, 129>; // 8 x f64 vector value
204 def v16f64 : VTVec<16, f64, 130>; // 16 x f64 vector value
205 def v32f64 : VTVec<32, f64, 131>; // 32 x f64 vector value
206 def v64f64 : VTVec<64, f64, 132>; // 64 x f64 vector value
207 def v128f64 : VTVec<128, f64, 133>; // 128 x f64 vector value
208 def v256f64 : VTVec<256, f64, 134>; // 256 x f64 vector value
[all …]
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVInstrInfoD.td243 // f64 -> f32, f32 -> f64
251 // f64 -> f32, f32 -> f64
259 // f64 -> f32, f32 -> f64
284 def : PatFprFpr<fcopysign, FSGNJ_D, FPR64, f64>;
471 defm Select_FPR64 : SelectCC_GPR_rrirr<FPR64, f64>;
473 def PseudoFROUND_D : PseudoFROUND<FPR64, f64>;
477 def : LdPat<load, FLD, f64>;
481 def : StPat<store, FSD, FPR64, f64>;
502 def PseudoFROUND_D_INX : PseudoFROUND<FPR64INX, f64>;
505 def : LdPat<load, LD, f64>;
[all …]
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/LoongArch/
H A DLoongArchFloat64InstrInfo.td230 defm : LdPat<load, FLD_D, f64>;
231 def : RegRegLdPat<load, FLDX_D, f64>;
235 defm : StPat<store, FST_D, FPR64, f64>;
236 def : RegRegStPat<store, FSTX_D, FPR64, f64>;
244 // f64 -> f32
246 // f32 -> f64
247 def : Pat<(f64 (fpextend FPR32:$src)), (FCVT_D_S FPR32:$src)>;
285 def : Pat<(f64 fpimm0), (MOVGR2FR_D R0)>;
286 def : Pat<(f64 fpimm0neg), (FNEG_D (MOVGR2FR_D R0))>;
290 def : Pat<(f64 fpimm0), (MOVGR2FRH_W (MOVGR2FR_W_64 R0), R0)>;
[all …]
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/CSKY/
H A DCSKYCallingConv.td49 CCIfType<[f64], CCCustom<"CC_CSKY_ABIV2_SOFT_64">>,
50 CCIfType<[f64], CCAssignToStack<8, 4>>
59 CCIfType<[f64], CCCustom<"Ret_CSKY_ABIV2_SOFT_64">>
71 CCIfType<[f64], CCAssignToReg<[F0_64, F1_64, F2_64, F3_64]>>,
72 CCIfType<[f64], CCAssignToStack<8, 4>>
81 CCIfType<[f64], CCAssignToReg<[F0_64]>>
/freebsd-14.2/contrib/llvm-project/compiler-rt/lib/builtins/arm/
H A Dtruncdfsf2vfp.S22 vcvt.f32.f64 s0, d0
25 vcvt.f32.f64 s15, d7 // convert double to single (trucate precision)
H A Dextendsfdf2vfp.S22 vcvt.f64.f32 d0, s0
25 vcvt.f64.f32 d7, s15 // convert single to double
H A Dfloatsidfvfp.S23 vcvt.f64.s32 d0, s0
26 vcvt.f64.s32 d7, s15 // convert 32-bit int in s15 to double in d7
H A Dfixunsdfsivfp.S23 vcvt.u32.f64 s0, d0
27 vcvt.u32.f64 s15, d7 // convert double to 32-bit int into s15
H A Dfloatunssidfvfp.S23 vcvt.f64.u32 d0, s0
26 vcvt.f64.u32 d7, s15 // convert 32-bit int in s15 to double in d7
H A Dfixdfsivfp.S22 vcvt.s32.f64 s0, d0
26 vcvt.s32.f64 s15, d7 // convert double to 32-bit int into s15
H A Dadddf3vfp.S20 vadd.f64 d0, d0, d1
24 vadd.f64 d6, d6, d7
H A Ddivdf3vfp.S21 vdiv.f64 d0, d0, d1
25 vdiv.f64 d5, d6, d7
H A Dmuldf3vfp.S21 vmul.f64 d0, d0, d1
25 vmul.f64 d6, d6, d7
H A Dsubdf3vfp.S21 vsub.f64 d0, d0, d1
25 vsub.f64 d6, d6, d7

123456789