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/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyInstrFloat.td19 !strconcat("f32.", name), f32Inst>;
30 !strconcat("f32.", name), f32Inst>;
76 def : Pat<(frint f32:$src), (NEAREST_F32 f32:$src)>;
80 def : Pat<(froundeven f32:$src), (NEAREST_F32 f32:$src)>;
93 def : Pat<(seteq f32:$lhs, f32:$rhs), (EQ_F32 f32:$lhs, f32:$rhs)>;
94 def : Pat<(setne f32:$lhs, f32:$rhs), (NE_F32 f32:$lhs, f32:$rhs)>;
95 def : Pat<(setlt f32:$lhs, f32:$rhs), (LT_F32 f32:$lhs, f32:$rhs)>;
96 def : Pat<(setle f32:$lhs, f32:$rhs), (LE_F32 f32:$lhs, f32:$rhs)>;
97 def : Pat<(setgt f32:$lhs, f32:$rhs), (GT_F32 f32:$lhs, f32:$rhs)>;
98 def : Pat<(setge f32:$lhs, f32:$rhs), (GE_F32 f32:$lhs, f32:$rhs)>;
[all …]
H A DWebAssemblyInstrConv.td185 "f32.convert_i32_s\t$dst, $src", "f32.convert_i32_s",
189 "f32.convert_i32_u\t$dst, $src", "f32.convert_i32_u",
201 "f32.convert_i64_s\t$dst, $src", "f32.convert_i64_s",
205 "f32.convert_i64_u\t$dst, $src", "f32.convert_i64_u",
222 "f32.demote_f64\t$dst, $src", "f32.demote_f64",
231 "f32.reinterpret_i32\t$dst, $src",
232 "f32.reinterpret_i32", 0xbe>;
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DVINTERPInstructions.td68 def VOP3_VINTERP_F32 : VOPProfile<[f32, f32, f32, f32]> {
114 VINTERP_Pseudo <"v_interp_p10_f16_f32", VOP3_VINTERP_F16<[f32, f32, f32, f32]>>;
116 VINTERP_Pseudo <"v_interp_p2_f16_f32", VOP3_VINTERP_F16<[f16, f32, f32, f32]>>;
121 VINTERP_Pseudo <"v_interp_p10_rtz_f16_f32", VOP3_VINTERP_F16<[f32, f32, f32, f32]>>;
123 VINTERP_Pseudo <"v_interp_p2_rtz_f16_f32", VOP3_VINTERP_F16<[f16, f32, f32, f32]>>;
129 (f32 (op
130 (VINTERPMods f32:$src0, i32:$src0_modifiers),
131 (VINTERPMods f32:$src1, i32:$src1_modifiers),
149 (pat[0] f32:$src0, i32:$src0_modifiers),
150 (pat[1] f32:$src1, i32:$src1_modifiers),
[all …]
H A DR600Instructions.td391 SDTCisVT<3, f32>, SDTCisVT<4, f32>, SDTCisVT<5, f32>,
392 SDTCisVT<6, f32>, SDTCisVT<7, f32>, SDTCisVT<8, f32>]>,
685 [(set f32:$dst, (fabs f32:$src0))]
692 [(set f32:$dst, (fneg f32:$src0))]
742 [(set f32:$dst, (selectcc f32:$src0, f32:$src1, FP_ONE, FP_ZERO, COND_OEQ))]
997 [(set f32:$dst, (any_fmad f32:$src0, f32:$src1, f32:$src2))]
1002 [(set f32:$dst, (fma f32:$src0, f32:$src1, f32:$src2))], VecALU
1010 [(set f32:$dst, (selectcc f32:$src0, FP_ZERO, f32:$src1, f32:$src2, COND_OEQ))]
1015 [(set f32:$dst, (selectcc f32:$src0, FP_ZERO, f32:$src1, f32:$src2, COND_OGT))]
1022 [(set f32:$dst, (selectcc f32:$src0, FP_ZERO, f32:$src1, f32:$src2, COND_OGE))]
[all …]
H A DR600RegisterInfo.td177 def R600_KC0_X : RegisterClass <"AMDGPU", [f32, i32], 32,
180 def R600_KC0_Y : RegisterClass <"AMDGPU", [f32, i32], 32,
183 def R600_KC0_Z : RegisterClass <"AMDGPU", [f32, i32], 32,
186 def R600_KC0_W : RegisterClass <"AMDGPU", [f32, i32], 32,
189 def R600_KC0 : RegisterClass <"AMDGPU", [f32, i32], 32,
193 def R600_KC1_X : RegisterClass <"AMDGPU", [f32, i32], 32,
196 def R600_KC1_Y : RegisterClass <"AMDGPU", [f32, i32], 32,
199 def R600_KC1_Z : RegisterClass <"AMDGPU", [f32, i32], 32,
202 def R600_KC1_W : RegisterClass <"AMDGPU", [f32, i32], 32,
205 def R600_KC1 : RegisterClass <"AMDGPU", [f32, i32], 32,
[all …]
H A DSIInstructions.td52 [(set f32:$vdst, (int_amdgcn_interp_p1 f32:$vsrc,
79 [(set f32:$vdst, (int_amdgcn_interp_p2 f32:$src0, f32:$vsrc,
1199 (f32 (fadd (AMDGPUfmul_legacy (VOP3NoMods f32:$src0),
1210 (f32 (int_amdgcn_fma_legacy (VOP3NoMods f32:$src0),
2251 (f32 (fpow (VOP3Mods f32:$src0, i32:$src0_mods), (VOP3Mods f32:$src1, i32:$src1_mods))),
2349 (fcopysign f32:$src0, f32:$src1),
2979 (fcanonicalize (f32 (VOP3Mods f32:$src, i32:$src_mods))),
3009 (fcanonicalize (f32 (VOP3Mods f32:$src, i32:$src_mods))),
3074 (fma (f32 (VOP3NoMods f32:$src0)),
3075 (f32 (VOP3NoMods f32:$src1)),
[all …]
H A DAMDGPUCallingConv.td25 CCIfInReg<CCIfType<[f32, i32, f16, i16, v2i16, v2f16, bf16, v2bf16] , CCAssignToReg<[
32 CCIfNotInReg<CCIfType<[f32, i32, f16, i16, v2i16, v2f16, bf16, v2bf16] , CCAssignToReg<[
39 CCIfType<[i32, f32, v2i16, v2f16, i16, f16, i1, bf16, v2bf16], CCAssignToStack<4, 4>>
46 CCIfNotInReg<CCIfType<[f32, i32, f16, i16, v2i16, v2f16, bf16, v2bf16] , CCAssignToReg<[
69 CCIfInReg<CCIfType<[f32, i32, f16, i16, v2i16, v2f16, bf16, v2bf16] , CCAssignToReg<[
112 CCIfType<[f32, f16, v2f16, bf16, v2bf16] , CCAssignToReg<[
191 CCIfInReg<CCIfType<[f32, i32, f16, i16, v2i16, v2f16, bf16, v2bf16] , CCAssignToReg<
195 CCIfType<[i32, f32, i16, f16, v2i16, v2f16, i1, bf16, v2bf16], CCAssignToReg<[
200 CCIfType<[i32, f32, v2i16, v2f16, i16, f16, i1, bf16, v2bf16], CCAssignToStack<4, 4>>
207 CCIfType<[i32, f32, i16, f16, v2i16, v2f16, bf16, v2bf16], CCAssignToReg<[
[all …]
/freebsd-14.2/lib/libc/arm/aeabi/
H A Daeabi_vfp_float.S37 vcmp.f32 s0, s1
45 vcmpe.f32 s0, s1
53 vcmpe.f32 s1, s0
61 vcmp.f32 s0, s1
72 vcmp.f32 s0, s1
83 vcmp.f32 s0, s1
94 vcmp.f32 s0, s1
105 vcmp.f32 s0, s1
116 vcmp.f32 s0, s1
133 vcvt.s32.f32 s0, s0
[all …]
/freebsd-14.2/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DValueTypes.td178 def v1f32 : VTVec<1, f32, 105>; // 1 x f32 vector value
179 def v2f32 : VTVec<2, f32, 106>; // 2 x f32 vector value
180 def v3f32 : VTVec<3, f32, 107>; // 3 x f32 vector value
181 def v4f32 : VTVec<4, f32, 108>; // 4 x f32 vector value
182 def v5f32 : VTVec<5, f32, 109>; // 5 x f32 vector value
183 def v6f32 : VTVec<6, f32, 110>; // 6 x f32 vector value
184 def v7f32 : VTVec<7, f32, 111>; // 7 x f32 vector value
185 def v8f32 : VTVec<8, f32, 112>; // 8 x f32 vector value
186 def v9f32 : VTVec<9, f32, 113>; // 9 x f32 vector value
187 def v10f32 : VTVec<10, f32, 114>; // 10 x f32 vector value
[all …]
/freebsd-14.2/contrib/llvm-project/llvm/include/llvm/Analysis/
H A DVecFuncs.def35 TLI_DEFINE_VECFUNC("llvm.fabs.f32", "vfabsf", FIXED(4), "_ZGV_LLVM_N4v")
38 TLI_DEFINE_VECFUNC("llvm.sqrt.f32", "vsqrtf", FIXED(4), "_ZGV_LLVM_N4v")
42 TLI_DEFINE_VECFUNC("llvm.exp.f32", "vexpf", FIXED(4), "_ZGV_LLVM_N4v")
45 TLI_DEFINE_VECFUNC("llvm.log.f32", "vlogf", FIXED(4), "_ZGV_LLVM_N4v")
48 TLI_DEFINE_VECFUNC("llvm.log10.f32", "vlog10f", FIXED(4), "_ZGV_LLVM_N4v")
53 TLI_DEFINE_VECFUNC("llvm.sin.f32", "vsinf", FIXED(4), "_ZGV_LLVM_N4v")
55 TLI_DEFINE_VECFUNC("llvm.cos.f32", "vcosf", FIXED(4), "_ZGV_LLVM_N4v")
219 TLI_DEFINE_VECFUNC("llvm.exp.f32", "__expf4", FIXED(4), "_ZGV_LLVM_N4v")
229 TLI_DEFINE_VECFUNC("llvm.log.f32", "__logf4", FIXED(4), "_ZGV_LLVM_N4v")
245 TLI_DEFINE_VECFUNC("llvm.sin.f32", "__sinf4", FIXED(4), "_ZGV_LLVM_N4v")
[all …]
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCInstrVSX.td1201 [(set f32:$XT, (any_fma f32:$XA, f32:$XB, f32:$XTi))]>,
2736 def : Pat<(f32 (fminnum_ieee f32:$A, f32:$B)),
2745 def : Pat<(f32 (fmaxnum_ieee f32:$A, f32:$B)),
2848 def : Pat<(v4f32 (build_vector f32:$A, f32:$A, f32:$A, f32:$A)),
2960 def : Pat<(v4f32 (build_vector f32:$A, f32:$B, f32:$C, f32:$D)),
3085 def : Pat<(v4f32 (build_vector f32:$D, f32:$C, f32:$B, f32:$A)),
3297 def : Pat<(PPCfnmsub f32:$A, f32:$B, f32:$C),
3299 def : Pat<(fneg (PPCfnmsub f32:$A, f32:$B, f32:$C)),
3301 def : Pat<(PPCfnmsub f32:$A, f32:$B, (fneg f32:$C)),
4077 def : Pat<(f32 (PPCxsmaxc f32:$XA, f32:$XB)),
[all …]
H A DPPCInstrSPE.td245 [(set f32:$RT, (any_fadd f32:$RA, f32:$RB))]>;
298 [(set f32:$RT, (any_fdiv f32:$RA, f32:$RB))]>;
302 [(set f32:$RT, (any_fmul f32:$RA, f32:$RB))]>;
314 [(set f32:$RT, (any_fsub f32:$RA, f32:$RB))]>;
830 def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETLT)),
832 def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETULT)),
834 def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETLE)),
838 def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETEQ)),
840 def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETGE)),
844 def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETGT)),
[all …]
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVInstrInfoZfbfmin.td21 : SDTypeProfile<1, 1, [SDTCisVT<0, bf16>, SDTCisVT<1, f32>]>;
23 : SDTypeProfile<1, 1, [SDTCisVT<0, f32>, SDTCisVT<1, bf16>]>;
53 // f32 -> bf16, bf16 -> f32
66 // bf16->[u]int. Round-to-zero must be used for the f32->int step, the
67 // rounding mode has no effect for bf16->f32.
77 // bf16->[u]int64. Round-to-zero must be used for the f32->int step, the
78 // rounding mode has no effect for bf16->f32.
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/CSKY/
H A DCSKYCallingConv.td45 CCIfType<[f32], CCAssignToReg<[R0, R1, R2, R3]>>,
46 CCIfType<[f32], CCAssignToStack<4, 4>>,
57 CCIfType<[f32], CCBitConvertToType<i32>>,
69 CCIfType<[f32], CCAssignToReg<[F0_32, F1_32, F2_32, F3_32]>>,
70 CCIfType<[f32], CCAssignToStack<4, 4>>,
80 CCIfType<[f32], CCAssignToReg<[F0_32]>>,
/freebsd-14.2/contrib/llvm-project/llvm/include/llvm/IR/
H A DIntrinsicsNVVM.td317 ["tf32"], [], ["f32"], []>.ret;
320 ["bf16"], [], ["f32"], []>.ret;
326 ["f16"], [], ["f16", "f32"], ["f16", "f32"]>.ret;
342 ["tf32"], [], ["f32"], []>.ret;
345 ["bf16"], [], ["f32"], []>.ret;
351 ["f16"], [], ["f16", "f32"], ["f16", "f32"]>.ret;
376 ["c", "d"], ["f32"]>.ret;
495 // m8n8k4 has no C=f32 D=f16 variant.
548 !eq(type,"f32"): llvm_float_ty);
1792 "llvm.nvvm.tex.1d.v4f32.f32">;
[all …]
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/LoongArch/
H A DLoongArchFloat32InstrInfo.td18 : SDTypeProfile<1, 1, [SDTCisVT<0, f32>, SDTCisVT<1, i64>]>;
20 : SDTypeProfile<1, 1, [SDTCisVT<0, i64>, SDTCisVT<1, f32>]>;
265 defm : LdPat<load, FLD_S, f32>;
266 def : RegRegLdPat<load, FLDX_S, f32>;
270 defm : StPat<store, FST_S, FPR32, f32>;
271 def : RegRegStPat<store, FSTX_S, FPR32, f32>;
275 def : Pat<(f32 fpimm0), (MOVGR2FR_W R0)>;
276 def : Pat<(f32 fpimm0neg), (FNEG_S (MOVGR2FR_W R0))>;
321 // int -> f32
324 // uint -> f32
[all …]
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/NVPTX/
H A DNVPTXIntrinsics.td2127 defm _f32 : ATOM2S_impl<OpStr, "f", "f32", f32, Float32Regs, f32imm, fpimm, f32,
3175 : TEX_CUBE<"tex.cube.v4.f32.f32", Float32Regs, Float32Regs>;
3262 : TEX_CUBE_ARRAY_LEVEL<"tex.level.acube.v4.f32.f32",
3291 : TLD4_2D<"tld4.r.2d.v4.f32.f32", Float32Regs, Float32Regs>;
3293 : TLD4_2D<"tld4.g.2d.v4.f32.f32", Float32Regs, Float32Regs>;
3438 : TEX_UNIFIED_1D_ARRAY_LEVEL<"tex.level.a1d.v4.f32.f32",
3466 : TEX_UNIFIED_1D_ARRAY_GRAD<"tex.grad.a1d.v4.f32.f32",
3590 : TEX_UNIFIED_2D_ARRAY_LEVEL<"tex.level.a2d.v4.f32.f32",
3618 : TEX_UNIFIED_2D_ARRAY_GRAD<"tex.grad.a2d.v4.f32.f32",
3736 : TEX_UNIFIED_CUBE_LEVEL<"tex.level.cube.v4.f32.f32",
[all …]
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMInstrVFP.td63 def vfp_f32f16imm : PatLeaf<(f32 fpimm), [{
76 def vfp_f32imm : Operand<f32>,
77 PatLeaf<(f32 fpimm), [{
1034 [(set (f32 SPR:$Sd), (node (f32 SPR:$Sm)))]>,
1051 def : InstAlias<!strconcat("vrint", opc, "$p.f32.f32\t$Sd, $Sm"),
1077 [(set (f32 SPR:$Sd), (node (f32 SPR:$Sm)))]>,
1093 def : InstAlias<!strconcat("vrint", opc, ".f32.f32\t$Sd, $Sm"),
2349 def : Pat<(fneg (fma (f32 SPR:$Sn), (f32 SPR:$Sm), (f32 SPR:$Sdin))),
2437 [(set (f32 SPR:$Sd),
2668 def : Pat<(f32 (vfp_f32f16imm:$imm)),
[all …]
H A DARMInstrCDE.td548 def : Pat<(f32 (int_arm_cde_vcx1 timm:$coproc, timm:$imm)),
549 (f32 (CDE_VCX1_fpsp p_imm:$coproc, imm_11b:$imm))>;
550 def : Pat<(f32 (int_arm_cde_vcx1a timm:$coproc, (f32 SPR:$acc), timm:$imm)),
557 def : Pat<(f32 (int_arm_cde_vcx2 timm:$coproc, (f32 SPR:$n), timm:$imm)),
558 (f32 (CDE_VCX2_fpsp p_imm:$coproc, SPR:$n, imm_6b:$imm))>;
559 def : Pat<(f32 (int_arm_cde_vcx2a timm:$coproc, (f32 SPR:$acc), (f32 SPR:$n),
568 def : Pat<(f32 (int_arm_cde_vcx3 timm:$coproc, (f32 SPR:$n), (f32 SPR:$m),
570 (f32 (CDE_VCX3_fpsp p_imm:$coproc, (f32 SPR:$n), (f32 SPR:$m),
572 def : Pat<(f32 (int_arm_cde_vcx3a timm:$coproc, (f32 SPR:$acc), (f32 SPR:$n),
573 (f32 SPR:$m), timm:$imm)),
[all …]
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsCallingConv.td86 CCIfType<[i32, f32], CCAssignToStack<4, 4>>,
104 // f32 are returned in registers F0, F2
105 CCIfType<[f32], CCAssignToReg<[F0, F2]>>,
152 CCIfType<[f32], CCAssignToRegWithShadow<[F12, F13, F14, F15,
164 CCIfType<[f32], CCAssignToStack<4, 8>>,
184 CCIfType<[f32], CCAssignToStack<4, 8>>,
213 // f32 are returned in registers F0, F2
214 CCIfType<[f32], CCAssignToReg<[F0, F2]>>,
281 CCIfType<[f32], CCIfSubtarget<"useOddSPReg()",
286 CCIfType<[f32], CCIfSubtarget<"noOddSPReg()",
[all …]
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Sparc/
H A DSparcCallingConv.td20 // i32 f32 arguments get passed in integer registers if there is space.
21 CCIfType<[i32, f32], CCAssignToReg<[I0, I1, I2, I3, I4, I5]>>,
35 CCIfType<[f32], CCAssignToReg<[F0, F1, F2, F3]>>,
115 CCIfInReg<CCIfType<[i32, f32], CCCustom<"CC_Sparc64_Half">>>,
126 // A single f32 return value always goes in %f0. The ABI doesn't specify what
127 // happens to multiple f32 return values outside a struct.
128 CCIfType<[f32], CCCustom<"RetCC_Sparc64_Half">>,
133 CCIfInReg<CCIfType<[i32, f32], CCCustom<"RetCC_Sparc64_Half">>>,
/freebsd-14.2/contrib/llvm-project/compiler-rt/lib/builtins/arm/
H A Dtruncdfsf2vfp.S22 vcvt.f32.f64 s0, d0
25 vcvt.f32.f64 s15, d7 // convert double to single (trucate precision)
H A Dextendsfdf2vfp.S22 vcvt.f64.f32 d0, s0
25 vcvt.f64.f32 d7, s15 // convert single to double
H A Daddsf3vfp.S21 vadd.f32 s0, s0, s1
25 vadd.f32 s14, s14, s15
H A Dsubsf3vfp.S22 vsub.f32 s0, s0, s1
26 vsub.f32 s14, s14, s15

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