| /freebsd-14.2/sys/contrib/device-tree/Bindings/edac/ |
| H A D | socfpga-eccmgr.txt | 38 l2-ecc@ffd08140 {
44 ocram-ecc@ffd08144 {
147 l2-ecc@ffd06010 {
154 ocram-ecc@ff8c3000 {
201 dma-ecc@ff8c8000 {
208 usb0-ecc@ff8c8800 {
216 qspi-ecc@ff8c8400 {
224 sdmmc-ecc@ff8c2c00 {
321 ocram-ecc@ff8cc000 {
363 dma-ecc@ff8c9000 {
[all …]
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| /freebsd-14.2/sys/contrib/device-tree/Bindings/mtd/ |
| H A D | mtk-nand.txt | 36 ecc-engine = <&bch>;
49 - nand-ecc-mode: the NAND ecc mode (check driver for supported modes)
65 E : nand-ecc-strength.
71 Q : nand-ecc-step-size.
127 nand-ecc-mode = "hw";
128 nand-ecc-strength = <24>;
129 nand-ecc-step-size = <1024>;
160 "mediatek,mt2701-ecc",
161 "mediatek,mt2712-ecc",
162 "mediatek,mt7622-ecc".
[all …]
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| H A D | mediatek,mtk-nfc.yaml | 37 ecc-engine:
49 nand-ecc-mode:
64 nand-ecc-step-size:
66 nand-ecc-strength:
79 nand-ecc-step-size:
81 nand-ecc-strength:
94 nand-ecc-step-size:
96 nand-ecc-strength:
105 - ecc-engine
126 ecc-engine = <&bch>;
[all …]
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| H A D | hisi504-nand.txt | 11 - nand-ecc-mode: Support none and hw ecc mode.
17 - nand-ecc-strength: Number of bits to correct per ECC step.
18 - nand-ecc-step-size: Number of data bytes covered by a single ECC step.
22 - nand-ecc-strength = <16>, nand-ecc-step-size = <1024>
34 nand-ecc-mode = "hw";
35 nand-ecc-strength = <16>;
36 nand-ecc-step-size = <1024>;
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| H A D | mxicy,nand-ecc-engine.yaml | 4 $id: http://devicetree.org/schemas/mtd/mxicy,nand-ecc-engine.yaml#
14 const: mxicy,nand-ecc-engine-rev3
46 nand-ecc-engine = <&ecc_engine0>;
50 ecc_engine0: ecc@43c40000 {
51 compatible = "mxicy,nand-ecc-engine-rev3";
65 nand-ecc-engine = <&ecc_engine1>;
70 nand-ecc-engine = <&spi_controller1>;
74 ecc_engine1: ecc@43c40000 {
75 compatible = "mxicy,nand-ecc-engine-rev3";
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| H A D | mediatek,nand-ecc-engine.yaml | 4 $id: http://devicetree.org/schemas/mtd/mediatek,nand-ecc-engine.yaml#
18 - mediatek,mt2701-ecc
19 - mediatek,mt2712-ecc
20 - mediatek,mt7622-ecc
21 - mediatek,mt7986-ecc
56 bch: ecc@1100e000 {
57 compatible = "mediatek,mt2701-ecc";
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| H A D | denali,nand.yaml | 40 ecc: ECC circuit clock
44 - const: ecc
79 nand-ecc-strength:
83 nand-ecc-step-size:
97 nand-ecc-strength:
102 nand-ecc-step-size:
116 nand-ecc-strength:
120 nand-ecc-step-size:
140 clock-names = "nand", "nand_x", "ecc";
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| H A D | gpmc-nand.txt | 28 "sw" 1-bit Hamming ecc code via software
31 "ham1" 1-bit Hamming ecc code
32 "bch4" 4-bit BCH ecc code
33 "bch8" 8-bit BCH ecc code
79 ti,nand-ecc-opt = "bch8";
131 '3' for HAM1_xx ecc schemes
132 '7' for BCH4_xx ecc schemes
133 '14' for BCH8_xx ecc schemes
134 '26' for BCH16_xx ecc schemes
137 trying to use BCH16 (ECC_BYTES=26) ecc-scheme.
[all …]
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| H A D | rockchip,nand-controller.yaml | 65 nand-ecc-mode:
68 nand-ecc-step-size:
71 nand-ecc-strength:
99 rockchip,boot-ecc-strength:
153 nand-ecc-mode = "hw";
154 nand-ecc-step-size = <1024>;
155 nand-ecc-strength = <16>;
158 rockchip,boot-ecc-strength = <16>;
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| H A D | nvidia-tegra20-nand.txt | 25 - nand-ecc-mode: String, operation mode of the NAND ecc mode. Currently only
27 - nand-ecc-algo: string, algorithm of NAND ECC.
31 - nand-ecc-strength: integer representing the number of bits to correct
36 - nand-ecc-maximize: See nand-controller.yaml
60 nand-ecc-algo = "bch";
61 nand-ecc-strength = <8>;
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| H A D | tango-nand.txt | 29 nand-ecc-strength = <14>;
30 nand-ecc-step-size = <1024>;
35 nand-ecc-strength = <14>;
36 nand-ecc-step-size = <1024>;
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| H A D | nand-chip.yaml | 25 nand-ecc-engine:
37 nand-use-soft-ecc-engine:
41 nand-no-ecc-engine:
45 nand-ecc-algo:
51 nand-ecc-strength:
57 nand-ecc-step-size:
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| H A D | vf610-nfc.txt | 29 - nand-ecc-mode: see nand-controller.yaml
32 - nand-ecc-strength: supported strengths are 24 and 32 bit (see nand-controller.yaml)
33 - nand-ecc-step-size: step size equals page size, currently only 2k pages are
54 nand-ecc-mode = "hw";
55 nand-ecc-strength = <32>;
56 nand-ecc-step-size = <2048>;
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| H A D | davinci-nand.txt | 42 - nand-ecc-mode: operation mode of the NAND ecc mode. ECC mode
48 - ti,davinci-ecc-bits: used ECC bits, currently supported 1 or 4.
58 - ti,davinci-ecc-mode: operation mode of the NAND ecc mode. ECC mode
86 nand-ecc-mode = "hw";
87 ti,davinci-ecc-bits = <4>;
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| H A D | ingenic,nand.yaml | 31 ecc-engine: true
81 ecc-engine = <&bch>;
95 nand-ecc-step-size = <1024>;
96 nand-ecc-strength = <24>;
97 nand-ecc-mode = "hw";
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| H A D | st,stm32-fmc2-nand.yaml | 29 - description: ecc DMA channel
35 - const: ecc
41 nand-ecc-step-size:
44 nand-ecc-strength:
118 dma-names = "tx", "rx", "ecc";
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| H A D | marvell-nand.txt | 47 - nand-ecc-mode: see nand-controller.yaml. Will use hardware ECC if not specified.
48 - nand-ecc-algo: see nand-controller.yaml. This property is essentially useful when
52 the NAND chip. This value may be overwritten with nand-ecc-strength
54 - nand-ecc-strength: see nand-controller.yaml.
55 - nand-ecc-step-size: see nand-controller.yaml. Marvell's NAND flash controller does
78 nand-ecc-mode = "hw";
81 nand-ecc-strength = <4>;
82 nand-ecc-step-size = <512>;
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| H A D | allwinner,sun4i-a10-nand.yaml | 57 nand-ecc-mode: true
59 nand-ecc-algo:
62 nand-ecc-step-size:
65 nand-ecc-strength:
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| /freebsd-14.2/sys/contrib/device-tree/src/arm64/intel/ |
| H A D | socfpga_agilex.dtsi | 603 ocram-ecc@ff8cc000 {
607 altr,ecc-parent = <&ocram>;
611 usb0-ecc@ff8c4000 {
613 "altr,socfpga-usb-ecc";
615 altr,ecc-parent = <&usb0>;
619 emac0-rx-ecc@ff8c0000 {
623 altr,ecc-parent = <&gmac0>;
627 emac0-tx-ecc@ff8c0400 {
631 altr,ecc-parent = <&gmac0>;
635 sdmmca-ecc@ff8c8c00 {
[all …]
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| /freebsd-14.2/sys/contrib/device-tree/src/arm64/altera/ |
| H A D | socfpga_stratix10.dtsi | 500 reset-names = "dwc2", "dwc2-ecc";
514 reset-names = "dwc2", "dwc2-ecc";
578 ocram-ecc@ff8cc000 {
582 altr,ecc-parent = <&ocram>;
586 usb0-ecc@ff8c4000 {
588 "altr,socfpga-usb-ecc";
590 altr,ecc-parent = <&usb0>;
594 emac0-rx-ecc@ff8c0000 {
598 altr,ecc-parent = <&gmac0>;
602 emac0-tx-ecc@ff8c0400 {
[all …]
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| /freebsd-14.2/sys/contrib/device-tree/src/arm/ |
| H A D | bcm5301x-nand-cs0-bch4.dtsi | 9 nand-ecc-algo = "bch";
10 nand-ecc-strength = <4>;
11 nand-ecc-step-size = <512>;
|
| H A D | bcm5301x-nand-cs0-bch1.dtsi | 11 nand-ecc-algo = "bch";
12 nand-ecc-strength = <1>;
13 nand-ecc-step-size = <512>;
|
| H A D | socfpga_arria10_socdk_sdmmc.dts | 19 sdmmca-ecc@ff8c2c00 {
20 compatible = "altr,socfpga-sdmmc-ecc";
22 altr,ecc-parent = <&mmc>;
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| H A D | bcm5301x-nand-cs0-bch8.dtsi | 14 nand-ecc-algo = "bch";
15 nand-ecc-strength = <8>;
16 nand-ecc-step-size = <512>;
|
| H A D | socfpga_arria10.dtsi | 709 l2-ecc@ffd06010 {
716 ocram-ecc@ff8c3000 {
723 emac0-rx-ecc@ff8c0800 {
726 altr,ecc-parent = <&gmac0>;
731 emac0-tx-ecc@ff8c0c00 {
739 sdmmca-ecc@ff8c2c00 {
742 altr,ecc-parent = <&mmc>;
749 dma-ecc@ff8c8000 {
752 altr,ecc-parent = <&pdma>;
757 usb0-ecc@ff8c8800 {
[all …]
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