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/freebsd-14.2/sys/arm/mv/clk/
H A Dperiph_clk_d.c68 struct clk_div_def *div2; in a37x0_periph_d_register_full_clk_dd() local
74 div2 = &device_def->clk_def.full_dd.div2; in a37x0_periph_d_register_full_clk_dd()
92 a37x0_periph_set_props(&div2->clkdef, &div1->clkdef.name, 1); in a37x0_periph_d_register_full_clk_dd()
93 error = a37x0_periph_create_div(clkdom, div2, in a37x0_periph_d_register_full_clk_dd()
99 parent_names[1] = div2->clkdef.name; in a37x0_periph_d_register_full_clk_dd()
231 struct clk_div_def *div2; in a37x0_periph_d_register_mdd() local
237 div2 = &device_def->clk_def.mdd.div2; in a37x0_periph_d_register_mdd()
253 a37x0_periph_set_props(&div2->clkdef, &div1->clkdef.name, 1); in a37x0_periph_d_register_mdd()
254 error = a37x0_periph_create_div(clkdom, div2, in a37x0_periph_d_register_mdd()
261 parent_names[1] = div2->clkdef.name; in a37x0_periph_d_register_mdd()
H A Dperiph.h82 .clk_def.full_dd.div2.i_width = 0x3, \
83 .clk_def.full_dd.div2.f_shift = 0x0, \
84 .clk_def.full_dd.div2.f_width = 0x0, \
85 .clk_def.full_dd.div2.div_flags = 0x0, \
200 .clk_def.mdd.div2.i_width = 0x3, \
201 .clk_def.mdd.div2.f_shift = 0x0, \
202 .clk_def.mdd.div2.f_width = 0x0, \
203 .clk_def.mdd.div2.div_flags = 0x0, \
204 .clk_def.mdd.div2.div_table = NULL, \
289 struct clk_div_def div2; member
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/freebsd-14.2/sys/contrib/device-tree/Bindings/clock/
H A Dqoriq-clock.txt165 clock-output-names = "pll0", "pll0-div2";
173 clock-output-names = "pll1", "pll1-div2";
181 clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
190 clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
199 clock-output-names = "platform-pll", "platform-pll-div2";
/freebsd-14.2/sys/contrib/device-tree/src/arm/
H A Dstih418-clock.dtsi136 clock-output-names = "clk-m-a9-ext2f-div2";
H A Dstih407-clock.dtsi131 clock-output-names = "clk-m-a9-ext2f-div2";
H A Dstih410-clock.dtsi136 clock-output-names = "clk-m-a9-ext2f-div2";
H A Dam33xx-clocks.dtsi269 dpll_ddr_m2_div2_ck: clock-dpll-ddr-m2-div2 {
442 dpll_core_m4_div2_ck: clock-dpll-core-m4-div2 {
H A Dam43xx-clocks.dtsi519 dpll_core_m4_div2_ck: clock-dpll-core-m4-div2 {
H A Dtegra30.dtsi1304 level2_trip: cpu-div2-throttle {
/freebsd-14.2/sys/contrib/device-tree/Bindings/iio/frequency/
H A Dadf4350.txt21 - adi,reference-div2-enable: Enables reference divider.
H A Dadi,adf4350.yaml55 adi,reference-div2-enable:
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVInstrInfoXCV.td465 def CV_CPLXMUL_R_DIV2 : CVSIMDRRWb<0b01010, 1, 0, 0b010, "cv.cplxmul.r.div2">;
466 def CV_CPLXMUL_I_DIV2 : CVSIMDRRWb<0b01010, 1, 1, 0b010, "cv.cplxmul.i.div2">;
477 def CV_SUBROTMJ_DIV2 : CVSIMDRR<0b01100, 1, 0, 0b010, "cv.subrotmj.div2">;
481 def CV_ADD_DIV2 : CVSIMDRR<0b01101, 1, 0, 0b010, "cv.add.div2">;
485 def CV_SUB_DIV2 : CVSIMDRR<0b01110, 1, 0, 0b010, "cv.sub.div2">;
/freebsd-14.2/sys/contrib/device-tree/Bindings/soc/fsl/
H A Dqman.txt162 clock-output-names = "platform-pll", "platform-pll-div2";
/freebsd-14.2/sys/contrib/device-tree/src/arm64/altera/
H A Dsocfpga_stratix10.dtsi101 cb_intosc_hs_div2_clk: cb-intosc-hs-div2-clk {
/freebsd-14.2/sys/contrib/device-tree/src/arm64/intel/
H A Dsocfpga_agilex.dtsi92 cb_intosc_hs_div2_clk: cb-intosc-hs-div2-clk {
/freebsd-14.2/sys/contrib/device-tree/src/arm64/qcom/
H A Dsm8550.dtsi41 bi_tcxo_div2: bi-tcxo-div2-clk {
49 bi_tcxo_ao_div2: bi-tcxo-ao-div2-clk {