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Searched refs:div1 (Results 1 – 6 of 6) sorted by relevance

/freebsd-14.2/sys/arm/xilinx/
H A Dzy7_slcr.c214 int div0, div1; in cgem_set_ref_clk() local
222 for (div1 = 1; div1 <= ZY7_SLCR_GEM_CLK_CTRL_DIVISOR1_MAX; div1++) { in cgem_set_ref_clk()
224 div1 / frequency; in cgem_set_ref_clk()
315 int div0, div1; in zy7_pl_fclk_set_freq() local
344 for (div1 = 1; div1 <= ZY7_SLCR_FPGA_CLK_CTRL_DIVISOR_MAX; div1++) { in zy7_pl_fclk_set_freq()
346 div1 / frequency; in zy7_pl_fclk_set_freq()
374 return (base_frequency / div0 / div1); in zy7_pl_fclk_set_freq()
381 int div0, div1; in zy7_pl_fclk_get_freq() local
422 if (div1 == 0) in zy7_pl_fclk_get_freq()
423 div1 = 1; in zy7_pl_fclk_get_freq()
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/freebsd-14.2/sys/arm/mv/clk/
H A Dperiph_clk_d.c67 struct clk_div_def *div1; in a37x0_periph_d_register_full_clk_dd() local
73 div1 = &device_def->clk_def.full_dd.div1; in a37x0_periph_d_register_full_clk_dd()
86 a37x0_periph_set_props(&div1->clkdef, &tbg_mux->clkdef.name, 1); in a37x0_periph_d_register_full_clk_dd()
87 error = a37x0_periph_create_div(clkdom, div1, in a37x0_periph_d_register_full_clk_dd()
92 a37x0_periph_set_props(&div2->clkdef, &div1->clkdef.name, 1); in a37x0_periph_d_register_full_clk_dd()
230 struct clk_div_def *div1; in a37x0_periph_d_register_mdd() local
236 div1 = &device_def->clk_def.mdd.div1; in a37x0_periph_d_register_mdd()
247 a37x0_periph_set_props(&div1->clkdef, &tbg_mux->clkdef.name, 1); in a37x0_periph_d_register_mdd()
248 error = a37x0_periph_create_div(clkdom, div1, in a37x0_periph_d_register_mdd()
253 a37x0_periph_set_props(&div2->clkdef, &div1->clkdef.name, 1); in a37x0_periph_d_register_mdd()
H A Dperiph.h74 .clk_def.full_dd.div1.i_width = 0x3, \
75 .clk_def.full_dd.div1.f_shift = 0x0, \
76 .clk_def.full_dd.div1.f_width = 0x0, \
77 .clk_def.full_dd.div1.div_flags = 0x0, \
192 .clk_def.mdd.div1.i_width = 0x3, \
193 .clk_def.mdd.div1.f_shift = 0x0, \
194 .clk_def.mdd.div1.f_width = 0x0, \
195 .clk_def.mdd.div1.div_flags = 0x0, \
196 .clk_def.mdd.div1.div_table = NULL, \
288 struct clk_div_def div1; member
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/freebsd-14.2/sys/contrib/device-tree/Bindings/clock/ti/
H A Ddpll.txt43 "mult-div1" - contains the multiplier / divider register base address
/freebsd-14.2/sys/contrib/device-tree/src/arm64/qcom/
H A Dmsm8996-oneplus-common.dtsi34 div1_mclk: div1-clk {
H A Dapq8096-db820c.dts550 audio_mclk: clk-div1-state {