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/freebsd-14.2/contrib/llvm-project/clang/include/clang/Basic/
H A DStmtNodes.td9 def Stmt : StmtNode<?, 1>;
10 def NullStmt : StmtNode<Stmt>;
11 def CompoundStmt : StmtNode<Stmt>;
12 def IfStmt : StmtNode<Stmt>;
13 def SwitchStmt : StmtNode<Stmt>;
14 def WhileStmt : StmtNode<Stmt>;
15 def DoStmt : StmtNode<Stmt>;
16 def ForStmt : StmtNode<Stmt>;
17 def GotoStmt : StmtNode<Stmt>;
20 def BreakStmt : StmtNode<Stmt>;
[all …]
H A DDeclNodes.td12 def Decl : DeclNode<?, "", 1>;
14 def PragmaComment : DeclNode<Decl>;
40 def Binding : DeclNode<Value>;
43 def MSGuid : DeclNode<Value>;
87 def ObjCImpl
99 def AccessSpec : DeclNode<Decl>;
100 def Friend : DeclNode<Decl>;
105 def Import : DeclNode<Decl>;
107 def OMPAllocate : DeclNode<Decl>;
108 def OMPRequires : DeclNode<Decl>;
[all …]
H A DDiagnosticGroups.td21 def ODR : DiagGroup<"odr">;
22 def : DiagGroup<"abi">;
65 def DeprecatedCoroutine :
67 def AlwaysInlineCoroutine :
125 def FloatConversion :
246 def DynamicExceptionSpec
453 def : DiagGroup<"import">;
485 def : DiagGroup<"inline">;
545 def NullPointerArithmetic
562 def FunctionDefInObjCContainer : DiagGroup<"function-def-in-objc-container">;
[all …]
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMSchedule.td60 def WriteALU : SchedWrite;
61 def ReadALU : SchedRead;
70 def WriteCMP : SchedWrite;
79 def ReadMUL : SchedRead;
86 def ReadMAC : SchedRead;
89 def WriteDIV : SchedWrite;
92 def WriteLd : SchedWrite;
94 def WriteST : SchedWrite;
97 def WriteBr : SchedWrite;
98 def WriteBrL : SchedWrite;
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/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/LoongArch/
H A DLoongArchLBTInstrInfo.td27 def ADC_B : ALU_3R<0x00300000>;
28 def ADC_H : ALU_3R<0x00308000>;
29 def ADC_W : ALU_3R<0x00310000>;
31 def SBC_B : ALU_3R<0x00320000>;
32 def SBC_H : ALU_3R<0x00328000>;
33 def SBC_W : ALU_3R<0x00330000>;
35 def ROTR_B : ALU_3R<0x001a0000>;
36 def ROTR_H : ALU_3R<0x001a8000>;
41 def RCR_B : ALU_3R<0x00340000>;
42 def RCR_H : ALU_3R<0x00348000>;
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/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCSchedule.td12 def IIC_IntSimple : InstrItinClass;
13 def IIC_IntGeneral : InstrItinClass;
14 def IIC_IntCompare : InstrItinClass;
15 def IIC_IntISEL : InstrItinClass;
16 def IIC_IntDivD : InstrItinClass;
17 def IIC_IntDivW : InstrItinClass;
18 def IIC_IntMFFS : InstrItinClass;
19 def IIC_IntMFVSCR : InstrItinClass;
20 def IIC_IntMTFSB0 : InstrItinClass;
21 def IIC_IntMTSRD : InstrItinClass;
[all …]
/freebsd-14.2/contrib/llvm-project/llvm/include/llvm/IR/
H A DIntrinsicsHexagonDep.td1063 def int_hexagon_A2_abs :
1072 def int_hexagon_A2_add :
1126 def int_hexagon_A2_and :
1159 def int_hexagon_A2_max :
1171 def int_hexagon_A2_min :
1183 def int_hexagon_A2_neg :
1192 def int_hexagon_A2_not :
1198 def int_hexagon_A2_or :
1204 def int_hexagon_A2_orp :
1210 def int_hexagon_A2_sat :
[all …]
H A DIntrinsicsAArch64.td47 def int_aarch64_frint32z
50 def int_aarch64_frint64z
53 def int_aarch64_frint32x
56 def int_aarch64_frint64x
514 def int_aarch64_neon_bfmmla
523 def int_aarch64_neon_bfcvt
525 def int_aarch64_neon_bfcvtn
527 def int_aarch64_neon_bfcvtn2
1610 def int_aarch64_sve_prf
2893 def int_aarch64_sve_psel
[all …]
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVSchedSiFiveP400.td241 def : WriteRes<WriteNop, []>;
248 def : ReadAdvance<ReadJmp, 0>;
249 def : ReadAdvance<ReadJalr, 0>;
250 def : ReadAdvance<ReadCSR, 0>;
253 def : ReadAdvance<ReadIALU, 0>;
259 def : ReadAdvance<ReadIDiv, 0>;
261 def : ReadAdvance<ReadIMul, 0>;
333 def : ReadAdvance<ReadCLZ, 0>;
335 def : ReadAdvance<ReadCTZ, 0>;
337 def : ReadAdvance<ReadCPOP, 0>;
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H A DRISCVSchedule.td23 def WriteNop : SchedWrite;
117 def ReadSFBJmp : SchedRead;
118 def ReadSFBALU : SchedRead;
121 def ReadJmp : SchedRead;
122 def ReadJalr : SchedRead;
123 def ReadCSR : SchedRead;
124 def ReadMemBase : SchedRead;
218 def : WriteRes<WriteFLD16, []>;
219 def : WriteRes<WriteFMA16, []>;
225 def : WriteRes<WriteFST16, []>;
[all …]
H A DRISCVSchedSyntacoreSCR1.td33 def SCR1_ALU : ProcResource<1>;
34 def SCR1_LSU : ProcResource<1>;
35 def SCR1_MUL : ProcResource<1>;
36 def SCR1_DIV : ProcResource<1>;
37 def SCR1_CFU : ProcResource<1>;
118 def : WriteRes<WriteFMA32, []>;
126 def : WriteRes<WriteSFB, []>;
130 def : WriteRes<WriteCSR, []>;
131 def : WriteRes<WriteNop, []>;
137 def : ReadAdvance<ReadJmp, 0>;
[all …]
H A DRISCVSchedRocket.td14 def RocketModel : SchedMachineModel {
172 def : WriteRes<WriteCSR, []>;
173 def : WriteRes<WriteNop, []>;
179 def : ReadAdvance<ReadJmp, 0>;
180 def : ReadAdvance<ReadJalr, 0>;
181 def : ReadAdvance<ReadCSR, 0>;
184 def : ReadAdvance<ReadIALU, 0>;
190 def : ReadAdvance<ReadIDiv, 0>;
192 def : ReadAdvance<ReadIMul, 0>;
208 def : ReadAdvance<ReadFMA32, 0>;
[all …]
H A DRISCVScheduleZb.td16 def WriteRotateImm : SchedWrite;
17 def WriteRotateImm32 : SchedWrite;
18 def WriteRotateReg : SchedWrite;
101 def : WriteRes<WriteCLZ, []>;
103 def : WriteRes<WriteCTZ, []>;
105 def : WriteRes<WriteCPOP, []>;
107 def : WriteRes<WriteREV8, []>;
108 def : WriteRes<WriteORCB, []>;
114 def : ReadAdvance<ReadCLZ, 0>;
116 def : ReadAdvance<ReadCTZ, 0>;
[all …]
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonIntrinsicsV5.td16 def: T_RP_pat<A2_addsp, int_hexagon_A2_addsp>;
17 def: T_PP_pat<A2_addpsat, int_hexagon_A2_addpsat>;
18 def: T_PP_pat<A2_minp, int_hexagon_A2_minp>;
19 def: T_PP_pat<A2_minup, int_hexagon_A2_minup>;
20 def: T_PP_pat<A2_maxp, int_hexagon_A2_maxp>;
21 def: T_PP_pat<A2_maxup, int_hexagon_A2_maxup>;
83 def: T_P_pat<S2_brevp, int_hexagon_S2_brevp>;
84 def: T_P_pat<S2_ct0p, int_hexagon_S2_ct0p>;
85 def: T_P_pat<S2_ct1p, int_hexagon_S2_ct1p>;
227 def: T_RR_pat<A4_orn, int_hexagon_A4_orn>;
[all …]
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUSearchableTables.td19 def RsrcIntrinsics : GenericTable {
51 def Gfx9BufferFormat : GcnBufferFormatTable {
64 def getGfx9BufferFormatInfo : SearchIndex {
68 def getGfx10BufferFormatInfo : SearchIndex {
217 def SourcesOfDivergence : GenericTable {
439 def : SourceOfDivergence<int_amdgcn_if>;
445 def : SourceOfDivergence<intr>;
451 def UniformIntrinsics : GenericTable {
461 def : AlwaysUniform<int_amdgcn_icmp>;
462 def : AlwaysUniform<int_amdgcn_fcmp>;
[all …]
H A DSISchedule.td13 def : PredicateProlog<[{
19 def WriteBranch : SchedWrite;
20 def WriteExport : SchedWrite;
21 def WriteLDS : SchedWrite;
22 def WriteSALU : SchedWrite;
23 def WriteSMEM : SchedWrite;
24 def WriteVMEM : SchedWrite;
27 def MIVGPRRead : SchedRead;
28 def MIMFMARead : SchedRead;
55 def Write64Bit : SchedWrite;
[all …]
/freebsd-14.2/contrib/llvm-project/clang/include/clang/AST/
H A DCommentHTMLNamedCharacterReferences.td15 def : NCR<"copy", 0x000A9>;
16 def : NCR<"COPY", 0x000A9>;
17 def : NCR<"trade", 0x02122>;
18 def : NCR<"TRADE", 0x02122>;
19 def : NCR<"reg", 0x000AE>;
20 def : NCR<"REG", 0x000AE>;
21 def : NCR<"lt", 0x0003C>;
22 def : NCR<"Lt", 0x0003C>;
23 def : NCR<"LT", 0x0003C>;
24 def : NCR<"gt", 0x0003E>;
[all …]
H A DCommentCommands.td52 def Begin : Command<name> {
57 def End : Command<endCommandName> {
90 def B : InlineCommand<"b">;
91 def C : InlineCommand<"c">;
92 def P : InlineCommand<"p">;
93 def A : InlineCommand<"a">;
94 def E : InlineCommand<"e">;
96 def Em : InlineCommand<"em">;
97 def Emoji : InlineCommand<"emoji">;
100 def Ref : InlineCommand<"ref">;
[all …]
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AVR/
H A DAVRDevices.td58 def FeatureSmallStack
107 def FeatureMultiplication
118 def FeatureTinyEncoding
124 def FeatureLowByteFirst
167 def FamilyAVR2
171 def FamilyAVR25
179 def FamilyAVR35
183 def FamilyAVR4 : Family<"avr4",
187 def FamilyAVR5 : Family<"avr5",
195 def FamilyTiny
[all …]
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsSchedule.td12 def ALU : FuncUnit;
13 def IMULDIV : FuncUnit;
19 def IIM16Alu : InstrItinClass;
20 def IIPseudo : InstrItinClass;
22 def II_ABS : InstrItinClass;
23 def II_ADDI : InstrItinClass;
24 def II_ADDIU : InstrItinClass;
25 def II_ADDIUPC : InstrItinClass;
26 def II_ADD : InstrItinClass;
27 def II_ADDU : InstrItinClass;
[all …]
H A DMipsScheduleGeneric.td16 def MipsGenericModel : SchedMachineModel {
974 def : InstRW<[GenericWriteFPUCmp],
976 def : InstRW<[GenericWriteFPUCmp],
979 def : InstRW<[GenericWriteFPUL],
982 def : InstRW<[GenericWriteFPUL],
985 def : InstRW<[GenericWriteFPUL],
988 def : InstRW<[GenericWriteFPUL],
991 def : InstRW<[GenericWriteFPUL],
994 def : InstRW<[GenericWriteFPUS],
1157 def : InstRW<[GenericDSPShort],
[all …]
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Sparc/
H A DSparcRegisterInfo.td228 def C0 : Ri< 0, "c0">;
229 def C1 : Ri< 1, "c1">;
230 def C2 : Ri< 2, "c2">;
231 def C3 : Ri< 3, "c3">;
232 def C4 : Ri< 4, "c4">;
233 def C5 : Ri< 5, "c5">;
234 def C6 : Ri< 6, "c6">;
235 def C7 : Ri< 7, "c7">;
236 def C8 : Ri< 8, "c8">;
237 def C9 : Ri< 9, "c9">;
[all …]
/freebsd-14.2/contrib/llvm-project/llvm/include/llvm/Target/GlobalISel/
H A DSelectionDAGCompat.td63 def : GINodeEquiv<G_ADD, add>;
64 def : GINodeEquiv<G_SUB, sub>;
65 def : GINodeEquiv<G_MUL, mul>;
72 def : GINodeEquiv<G_AND, and>;
73 def : GINodeEquiv<G_OR, or>;
74 def : GINodeEquiv<G_XOR, xor>;
75 def : GINodeEquiv<G_SHL, shl>;
76 def : GINodeEquiv<G_LSHR, srl>;
77 def : GINodeEquiv<G_ASHR, sra>;
102 def : GINodeEquiv<G_FMA, fma>;
[all …]
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64SchedExynosM4.td630 def : InstRW<[WriteST,
683 def : InstRW<[WriteVLD,
688 def : InstRW<[WriteVLD,
692 def : InstRW<[WriteVLD,
711 def : InstRW<[WriteVST,
718 def : InstRW<[WriteVST,
724 def : InstRW<[WriteVST,
839 def : InstRW<[WriteVLD,
842 def : InstRW<[WriteVLD,
871 def : InstRW<[WriteVLD,
[all …]
H A DAArch64SchedExynosM3.td518 def : InstRW<[M3WriteLD,
521 def : InstRW<[M3WriteLB,
533 def : InstRW<[WriteST,
568 def : InstRW<[WriteVLD,
573 def : InstRW<[WriteVLD,
577 def : InstRW<[WriteVLD,
590 def : InstRW<[WriteVST,
597 def : InstRW<[WriteVST,
602 def : InstRW<[WriteVST,
794 def : InstRW<[WriteVST,
[all …]

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