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/freebsd-14.2/contrib/bmake/unit-tests/
H A Ddotwait.mk5 TESTS= simple recursive shared cycle
58 cycle: cycle.1.99 .WAIT cycle.2.99
59 cycle.2.99: cycle.2.98 _ECHOUSE
60 cycle.2.98: cycle.2.97 _ECHOUSE
61 cycle.2.97: cycle.2.99 _ECHOUSE
/freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/
H A DScoreboardHazardRecognizer.cpp117 int cycle = Stalls; in getHazardType() local
134 int StageCycle = cycle + (int)i; in getHazardType()
165 cycle += IS->getNextCycles(); in getHazardType()
184 unsigned cycle = 0; in EmitInstruction() local
193 assert(((cycle + i) < RequiredScoreboard.getDepth()) && in EmitInstruction()
200 freeUnits &= ~ReservedScoreboard[cycle + i]; in EmitInstruction()
204 freeUnits &= ~RequiredScoreboard[cycle + i]; in EmitInstruction()
216 RequiredScoreboard[cycle + i] |= freeUnit; in EmitInstruction()
218 ReservedScoreboard[cycle + i] |= freeUnit; in EmitInstruction()
222 cycle += IS->getNextCycles(); in EmitInstruction()
/freebsd-14.2/sys/contrib/device-tree/Bindings/input/
H A Dpwm-vibrator.yaml14 strength increases based on the duty cycle of the enable PWM channel
15 (100% duty cycle meaning strongest vibration, 0% meaning no vibration).
18 driven at fixed duty cycle. If available this is can be used to increase
37 direction-duty-cycle-ns:
39 Duty cycle of the direction PWM channel in nanoseconds,
56 direction-duty-cycle-ns = <1000000000>;
H A Dpwm-vibrator.txt4 strength increases based on the duty cycle of the enable PWM channel
5 (100% duty cycle meaning strongest vibration, 0% meaning no vibration).
8 driven at fixed duty cycle. If available this is can be used to increase
18 - direction-duty-cycle-ns: Duty cycle of the direction PWM channel in
64 direction-duty-cycle-ns = <1000000000>;
/freebsd-14.2/usr.bin/gprof/
H A Dgprof.callg31 its membership in a cycle, if any.
58 parent's membership in a cycle, if any.
84 membership in a cycle, if any.
92 children) in the same cycle as the function. If
93 the function (or child) is a member of a cycle,
96 cycle as a whole.
103 cycle listings:
104 the cycle as a whole is listed with the same
106 the members of the cycle, and their contributions
107 to the time and call counts of the cycle.
H A Darcs.c358 int cycle; in cyclelink() local
386 cycle = 0; in cyclelink()
391 cycle += 1; in cyclelink()
392 cyclenlp = &cyclenl[cycle]; in cyclelink()
405 cyclenlp -> cycleno = cycle; /* internal number of cycle on */ in cyclelink()
414 printf( " is the head of cycle %d\n" , cycle ); in cyclelink()
421 memberp -> cycleno = cycle; in cyclelink()
433 if ( arcp -> arc_parentp -> cycleno == cycle ) { in cyclelink()
762 int cycle; in cycletime() local
766 for ( cycle = 1 ; cycle <= ncycle ; cycle += 1 ) { in cycletime()
[all …]
/freebsd-14.2/sys/contrib/device-tree/Bindings/regulator/
H A Dpwm-regulator.txt7 predefined voltage <=> duty-cycle values must be
10 Intermediary duty-cycle values which would normally
19 appropriate duty-cycle values. This allows for a much
22 assumption that a %50 duty-cycle value will cause the
35 Second cell is duty-cycle in percent (%)
38 - pwm-dutycycle-unit: Integer value encoding the duty cycle unit. If not
46 Duty cycle values are expressed in pwm-dutycycle-unit.
71 * Inverted PWM logic, and the duty cycle range is limited
H A Dpwm-regulator.yaml19 duty-cycle values must be provided via DT. Limitations are that the
21 Intermediary duty-cycle values which would normally allow finer grained
29 appropriate duty-cycle values. This allows for a much more fine grained
31 make an assumption that a %50 duty-cycle value will cause the regulator
54 - description: duty-cycle in percent (%)
63 Integer value encoding the duty cycle unit. If not
74 Duty cycle values are expressed in pwm-dutycycle-unit.
103 * Inverted PWM logic, and the duty cycle range is limited
/freebsd-14.2/usr.bin/tsort/tests/
H A Dtsort_test.sh33 atf_test_case cycle
56 atf_check -e match:cycle -o file:output tsort input
57 atf_check -e match:cycle -o file:output tsort <input
65 atf_add_test_case cycle
/freebsd-14.2/sys/contrib/device-tree/Bindings/mtd/
H A Dgpmc-nor.txt21 - gpmc,access-ns: Start cycle to first data capture (read access)
22 - gpmc,rd-cycle-ns: Total read cycle time
23 - gpmc,wr-cycle-ns: Total write cycle time
70 gpmc,rd-cycle-ns = <186>;
71 gpmc,wr-cycle-ns = <186>;
/freebsd-14.2/sys/contrib/device-tree/Bindings/spi/
H A Drenesas,sh-msiof.yaml118 - 50 # 0.5-clock-cycle delay
119 - 100 # 1-clock-cycle delay
120 - 150 # 1.5-clock-cycle delay
121 - 200 # 2-clock-cycle delay
128 - 50 # 0.5-clock-cycle delay
129 - 100 # 1-clock-cycle delay
130 - 150 # 1.5-clock-cycle delay
131 - 200 # 2-clock-cycle delay
132 - 300 # 3-clock-cycle delay
/freebsd-14.2/contrib/ncurses/menu/
H A Dm_global.c387 bool cycle = (menu->opt & O_NONCYCLIC) ? FALSE : TRUE; in _nc_Link_Items() local
405 (cycle ? menu->items[(Last_in_Row >= Number_Of_Items) ? in _nc_Link_Items()
414 (cycle ? menu->items[row * Number_Of_Columns] : in _nc_Link_Items()
421 (cycle ? menu->items[(Last_in_Column >= Number_Of_Items) ? in _nc_Link_Items()
429 (cycle ? menu->items[(row + 1) < menu->rows ? in _nc_Link_Items()
454 (cycle ? (Last_in_Column >= Number_Of_Items) ? in _nc_Link_Items()
462 (cycle ? menu->items[row] : (ITEM *)0); in _nc_Link_Items()
468 (cycle ? in _nc_Link_Items()
479 (cycle ? in _nc_Link_Items()
/freebsd-14.2/sys/contrib/device-tree/Bindings/net/
H A Dgpmc-eth.txt36 - gpmc,access-ns: Start cycle to first data capture (read access)
37 - gpmc,rd-cycle-ns: Total read cycle time
38 - gpmc,wr-cycle-ns: Total write cycle time
78 gpmc,rd-cycle-ns = <186>;
79 gpmc,wr-cycle-ns = <186>;
/freebsd-14.2/sys/contrib/device-tree/src/arm/
H A Domap3430-sdp.dts73 gpmc,rd-cycle-ns = <186>;
74 gpmc,wr-cycle-ns = <186>;
123 gpmc,rd-cycle-ns = <72>;
124 gpmc,wr-cycle-ns = <72>;
169 gpmc,rd-cycle-ns = <108>;
170 gpmc,wr-cycle-ns = <96>;
/freebsd-14.2/sys/contrib/device-tree/Bindings/memory-controllers/
H A Dmvebu-devbus.txt40 cycle from a slow device.
53 ALE[0] to the cycle that the first read data is sampled
57 - devbus,acc-next-ps: Defines the time delay between the cycle that
58 samples data N and the cycle that samples data N+1
64 DEV_OEn and DEV_CSn are asserted at the same cycle.
73 DEV_OEn and DEV_CSn are de-asserted at the same cycle
74 (the cycle of the last data sample).
76 DEV_OEn is always de-asserted the next cycle after
85 - devbus,ale-wr-ps: Defines the time delay from the ALE[0] negation cycle
H A Dti,gpmc-child.yaml92 # Access time and cycle time timings (in nanoseconds) corresponding to
99 description: Start-cycle to first data valid delay
102 gpmc,rd-cycle-ns:
103 description: Total read cycle time
106 gpmc,wr-cycle-ns:
107 description: Total write cycle time
/freebsd-14.2/sys/contrib/device-tree/Bindings/leds/backlight/
H A Dpwm-backlight.txt19 0 will do. The actual brightness level (PWM duty cycle)
21 cycle (darkest/off), while the last value in the array
22 represents a 100% duty cycle (brightest).
27 resolution pwm duty cycle can be used without
H A Dpwm-backlight.yaml46 level (PWM duty cycle) will be interpolated from these values. 0 means a
47 0% duty cycle (darkest/off), while the last value in the array represents
48 a 100% duty cycle (brightest).
60 table. This way a high resolution pwm duty cycle can be used without
/freebsd-14.2/sys/dev/pwm/
H A Dpwmbus_if.m51 # Config the period (Total number of cycle in ns) and
52 # the duty (active number of cycle in ns)
62 # Get the period (Total number of cycle in ns) and
63 # the duty (active number of cycle in ns)
/freebsd-14.2/usr.sbin/fwcontrol/
H A Dfwdv.c259 int system=-1, pad_acc, cycle_acc, cycle, f_frac; in dvsend() local
350 cycle = 1; in dvsend()
351 cycle_acc = frame_cycle[system].d * cycle; in dvsend()
367 ciph->fdf.dv.cyc = htons(cycle << 12 | f_frac); in dvsend()
384 cycle ++; in dvsend()
392 cycle ++; in dvsend()
/freebsd-14.2/lib/libthr/thread/
H A Dthr_barrier.c135 int64_t cycle; in _pthread_barrier_wait() local
158 cycle = bar->b_cycle; in _pthread_barrier_wait()
164 } while (cycle == bar->b_cycle); in _pthread_barrier_wait()
H A Dthr_resume_np.c94 thread->cycle++; in resume_common()
95 _thr_umtx_wake(&thread->cycle, 1, 0); in resume_common()
/freebsd-14.2/sys/contrib/device-tree/src/arm64/broadcom/stingray/
H A Dstingray-board-base.dtsi38 full-pwr-cycle;
42 full-pwr-cycle;
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMScheduleA8.td95 // Result written in E5, but that is relative to the last cycle of multicycle,
124 // FIXME: lsl by 2 takes 1 cycle.
151 // FIXME: A8_LSPipe cycle time is dynamic, this assumes 3 to 4 registers.
229 // FIXME: A8_LSPipe cycle time is dynamic, this assumes 3 to 4 registers.
393 // FIXME: A8_LSPipe cycle time is dynamic, this assumes 3 to 4 registers.
859 // Quad-register Permute (3 cycle issue)
929 // Double-register Integer Binary (4 cycle)
933 // Quad-register Integer Binary (4 cycle)
962 // Double-register Integer Shift (4 cycle)
966 // Quad-register Integer Shift (4 cycle)
[all …]
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCScheduleP9.td161 // Each execution and branch slice can receive up to two iops per cycle
192 // However, the ALU unit is only ever busy for 1 cycle at a time and may
193 // receive new instructions each cycle.
324 // Three cycle permute operations.
331 // Stores are listed as having a single cycle of latency. This is not
332 // completely accurate since it takes more than 1 cycle to actually store
334 // considered complete after one cycle.
384 // 2 or 5 cycle latencies for the branch unit.
393 // 6 cycle latency for the crypto unit

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