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Searched refs:createQTuple (Results 1 – 2 of 2) sorted by relevance

/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64ISelDAGToDAG.cpp348 SDValue createQTuple(ArrayRef<SDValue> Vecs);
1382 SDValue AArch64DAGToDAGISel::createQTuple(ArrayRef<SDValue> Regs) { in createQTuple() function in AArch64DAGToDAGISel
1453 SDValue RegSeq = createQTuple(Regs); in SelectTable()
2021 SDValue RegSeq = Is128Bit ? createQTuple(Regs) : createDTuple(Regs); in SelectStore()
2085 SDValue RegSeq = Is128Bit ? createQTuple(Regs) : createDTuple(Regs); in SelectPostStore()
2144 SDValue RegSeq = createQTuple(Regs); in SelectLoadLane()
2182 SDValue RegSeq = createQTuple(Regs); in SelectPostLoadLane()
2236 SDValue RegSeq = createQTuple(Regs); in SelectStoreLane()
2264 SDValue RegSeq = createQTuple(Regs); in SelectPostStoreLane()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/
H A DAArch64InstructionSelector.cpp717 static Register createQTuple(ArrayRef<Register> Regs, MachineIRBuilder &MIB) { in createQTuple() function
5279 auto RegSeq = createQTuple(Regs, MIB); in selectShuffleVector()
6055 Register Tuple = createQTuple(Regs, MIB); in selectVectorLoadLaneIntrinsic()
6096 Register Tuple = Ty.getSizeInBits() == 128 ? createQTuple(Regs, MIB) in selectVectorStoreIntrinsic()
6120 Register Tuple = createQTuple(Regs, MIB); in selectVectorStoreLaneIntrinsic()