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Searched refs:composeSubRegIndices (Results 1 – 8 of 8) sorted by relevance

/freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/
H A DTargetRegisterInfo.cpp351 unsigned FinalA = composeSubRegIndices(IA.getSubReg(), SubA); in getCommonSuperRegClass()
360 unsigned FinalB = composeSubRegIndices(IB.getSubReg(), SubB); in getCommonSuperRegClass()
H A DRegisterCoalescer.cpp427 DstSub = tri.composeSubRegIndices(MI->getOperand(0).getSubReg(), in INITIALIZE_PASS_DEPENDENCY()
583 return TRI.composeSubRegIndices(SrcIdx, SrcSub) == in isCoalescable()
584 TRI.composeSubRegIndices(DstIdx, DstSub); in isCoalescable()
1347 unsigned NewDstIdx = TRI->composeSubRegIndices(CP.getSrcIdx(), in reMaterializeTrivialDef()
1870 unsigned SubUseIdx = TRI->composeSubRegIndices(SubIdx, MO.getSubReg()); in updateRegDefsUses()
2656 TRI->composeSubRegIndices(SubIdx, MO.getSubReg())); in computeWriteLanes()
3119 unsigned S = TRI->composeSubRegIndices(SubIdx, MO.getSubReg()); in usesLanes()
H A DDetectDeadLanes.cpp93 SrcSubIdx = TRI.composeSubRegIndices(SubReg, SrcSubIdx); in isCrossCopy()
H A DTailDuplicator.cpp446 TRI->composeSubRegIndices(VI->second.SubReg, MO.getSubReg())); in duplicateInstruction()
H A DMachineOperand.cpp87 SubIdx = TRI.composeSubRegIndices(SubIdx, getSubReg()); in substVirtReg()
/freebsd-14.2/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DTargetRegisterInfo.h675 unsigned composeSubRegIndices(unsigned a, unsigned b) const { in composeSubRegIndices() function
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUInstructionSelector.cpp258 unsigned ComposedSubIdx = TRI.composeSubRegIndices(MO.getSubReg(), SubIdx); in getSubOperand64()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.cpp2383 SubRegIdx = TRI->composeSubRegIndices(SubRegIdx, in decomposeSubvectorInsertExtractToSubRegs()