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/freebsd-14.2/sys/contrib/dev/rtw88/
H A Dcoex.h330 const struct rtw_chip_info *chip = rtwdev->chip; in rtw_coex_set_init() local
332 chip->ops->coex_set_init(rtwdev); in rtw_coex_set_init()
338 const struct rtw_chip_info *chip = rtwdev->chip; in rtw_coex_set_ant_switch() local
340 if (!chip->ops->coex_set_ant_switch) in rtw_coex_set_ant_switch()
348 const struct rtw_chip_info *chip = rtwdev->chip; in rtw_coex_set_gnt_fix() local
350 chip->ops->coex_set_gnt_fix(rtwdev); in rtw_coex_set_gnt_fix()
355 const struct rtw_chip_info *chip = rtwdev->chip; in rtw_coex_set_gnt_debug() local
362 const struct rtw_chip_info *chip = rtwdev->chip; in rtw_coex_set_rfe_type() local
364 chip->ops->coex_set_rfe_type(rtwdev); in rtw_coex_set_rfe_type()
369 const struct rtw_chip_info *chip = rtwdev->chip; in rtw_coex_set_wl_tx_power() local
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H A Dcoex.c16 const struct rtw_chip_info *chip = rtwdev->chip; in rtw_coex_next_rssi_state() local
39 const struct rtw_chip_info *chip = rtwdev->chip; in rtw_coex_limited_tx() local
368 const struct rtw_chip_info *chip = rtwdev->chip; in rtw_coex_write_scbd() local
403 const struct rtw_chip_info *chip = rtwdev->chip; in rtw_coex_read_scbd() local
413 const struct rtw_chip_info *chip = rtwdev->chip; in rtw_coex_check_rfk() local
492 const struct rtw_chip_info *chip = rtwdev->chip; in rtw_coex_monitor_bt_enable() local
527 const struct rtw_chip_info *chip = rtwdev->chip; in rtw_coex_update_wl_link_info() local
708 const struct rtw_chip_info *chip = rtwdev->chip; in rtw_coex_update_bt_link_info() local
808 const struct rtw_chip_info *chip = rtwdev->chip; in rtw_coex_update_wl_ch_info() local
935 const struct rtw_chip_info *chip = rtwdev->chip; in rtw_coex_coex_ctrl_owner() local
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H A Dphy.c141 const struct rtw_chip_info *chip = rtwdev->chip; in rtw_phy_adaptivity_set_mode() local
168 const struct rtw_chip_info *chip = rtwdev->chip; in rtw_phy_adaptivity_init() local
183 const struct rtw_chip_info *chip = rtwdev->chip; in rtw_phy_cfo_init() local
202 const struct rtw_chip_info *chip = rtwdev->chip; in rtw_phy_init() local
229 const struct rtw_chip_info *chip = rtwdev->chip; in rtw_phy_dig_write() local
248 const struct rtw_chip_info *chip = rtwdev->chip; in rtw_phy_stat_false_alarm() local
606 const struct rtw_chip_info *chip = rtwdev->chip; in rtw_phy_dpk_track() local
662 const struct rtw_chip_info *chip = rtwdev->chip; in rtw_phy_cfo_track() local
723 const struct rtw_chip_info *chip = rtwdev->chip; in rtw_phy_cck_pd() local
898 const struct rtw_chip_info *chip = rtwdev->chip; in rtw_phy_read_rf() local
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H A Dmac.c273 const struct rtw_chip_info *chip = rtwdev->chip; in rtw_mac_power_switch() local
309 pwr_seq = pwr_on ? chip->pwr_on_seq : chip->pwr_off_seq; in rtw_mac_power_switch()
640 const struct rtw_chip_info *chip = rtwdev->chip; in download_firmware_to_mem() local
1005 const struct rtw_chip_info *chip = rtwdev->chip; in __rtw_mac_flush_prio_queue() local
1067 const struct rtw_chip_info *chip = rtwdev->chip; in txdma_queue_mapping() local
1073 rqpn = &chip->rqpn_table[1]; in txdma_queue_mapping()
1118 const struct rtw_chip_info *chip = rtwdev->chip; in set_trx_fifo_info() local
1173 const struct rtw_chip_info *chip = rtwdev->chip; in __priority_queue_cfg() local
1204 const struct rtw_chip_info *chip = rtwdev->chip; in __priority_queue_cfg_legacy() local
1230 const struct rtw_chip_info *chip = rtwdev->chip; in priority_queue_cfg() local
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H A Dmain.c410 const struct rtw_chip_info *chip = rtwdev->chip; in rtw_fwcd_prep() local
867 const struct rtw_chip_info *chip = rtwdev->chip; in rtw_set_channel() local
911 const struct rtw_chip_info *chip = rtwdev->chip; in rtw_chip_prepare_tx() local
980 const struct rtw_chip_info *chip = rtwdev->chip; in rtw_hw_config_rf_ant_num() local
1333 const struct rtw_chip_info *chip = rtwdev->chip; in rtw_wait_firmware_completion() local
1354 const struct rtw_chip_info *chip = rtwdev->chip; in rtw_update_lps_deep_mode() local
1373 const struct rtw_chip_info *chip = rtwdev->chip; in rtw_power_on() local
1562 const struct rtw_chip_info *chip = rtwdev->chip; in rtw_init_ht_cap() local
1715 const struct rtw_chip_info *chip = rtwdev->chip; in rtw_set_txrx_1ss() local
1842 const struct rtw_chip_info *chip = rtwdev->chip; in rtw_chip_parameter_setup() local
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H A Dbf.h98 if (rtwdev->chip->ops->config_bfee) in rtw_chip_config_bfee()
99 rtwdev->chip->ops->config_bfee(rtwdev, vif, bfee, enable); in rtw_chip_config_bfee()
106 if (rtwdev->chip->ops->set_gid_table) in rtw_chip_set_gid_table()
107 rtwdev->chip->ops->set_gid_table(rtwdev, vif, conf); in rtw_chip_set_gid_table()
113 if (rtwdev->chip->ops->cfg_csi_rate) in rtw_chip_cfg_csi_rate()
114 rtwdev->chip->ops->cfg_csi_rate(rtwdev, rssi, cur_rate, in rtw_chip_cfg_csi_rate()
/freebsd-14.2/sys/dev/wbwd/
H A Dwbwd.c101 enum chips chip; member
127 enum chips chip; member
137 .chip = w83627s,
197 .chip = nct6775,
202 .chip = nct6776,
207 .chip = nct6102,
212 .chip = nct6779,
217 .chip = nct6791,
222 .chip = nct6792,
227 .chip = nct6793,
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/freebsd-14.2/sys/dev/ata/chipsets/
H A Data-acerlabs.c112 switch (ctlr->chip->cfg2) { in ata_ali_chipinit()
114 ctlr->channels = ctlr->chip->cfg1; in ata_ali_chipinit()
143 if (ctlr->chip->chiprev < 0xc7) in ata_ali_chipinit()
152 if (ctlr->chip->chiprev <= 0xc4) in ata_ali_chipinit()
178 if (ctlr->chip->cfg2 == ALI_SATA) { in ata_ali_chipdeinit()
202 if (ctlr->chip->cfg2 & ALI_NEW && ctlr->chip->chiprev < 0xc7) in ata_ali_ch_attach()
205 if (ctlr->chip->chiprev <= 0xc4) { in ata_ali_ch_attach()
210 if (ctlr->chip->cfg2 & ALI_NEW) in ata_ali_ch_attach()
273 if (ctlr->chip->chiprev == 0xc3 || ctlr->chip->chiprev == 0xc2) { in ata_ali_reset()
308 if (ctlr->chip->cfg2 & ALI_NEW && ctlr->chip->chiprev < 0xc7) { in ata_ali_setmode()
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H A Data-siliconimage.c111 switch (ctlr->chip->cfg1) { in ata_sii_chipinit()
122 if (ctlr->chip->cfg2 & SII_SETCLK) { in ata_sii_chipinit()
128 ctlr->chip->text); in ata_sii_chipinit()
132 if (ctlr->chip->cfg2 & SII_4CH) { in ata_sii_chipinit()
149 if (ctlr->chip->max_dma >= ATA_SA150) { in ata_sii_chipinit()
185 if (ctlr->chip->cfg2 & SII_INTR) in ata_cmd_ch_attach()
224 mode = min(mode, ctlr->chip->max_dma); in ata_cmd_setmode()
281 if (ctlr->chip->cfg2 & SII_BUG) { in ata_sii_ch_attach()
289 if (ctlr->chip->cfg2 & SII_SETCLK) in ata_sii_ch_attach()
363 mode = min(mode, ctlr->chip->max_dma); in ata_sii_setmode()
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H A Data-promise.c208 ctlr->chip = idx; in ata_promise_probe()
222 switch (ctlr->chip->cfg1) { in ata_promise_chipinit()
255 if (ctlr->chip->cfg2 == PR_SX4X) { in ata_promise_chipinit()
304 switch (ctlr->chip->cfg2) { in ata_promise_chipinit()
336 if ((ctlr->chip->cfg2 == PR_SATA2) || (ctlr->chip->cfg2 == PR_CMBO2)) in ata_promise_chipinit()
365 if (ctlr->chip->cfg1 == PR_NEW) { in ata_promise_ch_attach()
470 switch (ctlr->chip->cfg1) { in ata_promise_setmode()
501 if (ctlr->chip->cfg1 < PR_TX) in ata_promise_setmode()
565 if (ctlr->chip->cfg2 & PR_SX4X) { in ata_promise_mio_ch_attach()
618 switch (ctlr->chip->cfg2) { in ata_promise_mio_status()
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H A Data-via.c132 if (!(ctlr->chip = ata_find_chip(dev, ids, -99))) in ata_via_probe()
136 if (!(ctlr->chip = ata_match_chip(dev, new_ids))) in ata_via_probe()
154 if (ctlr->chip->cfg2 & VIASATA) { in ata_via_chipinit()
162 if (ctlr->chip->max_dma >= ATA_SA150) { in ata_via_chipinit()
171 if (ctlr->chip->cfg2 & VIABAR) { in ata_via_chipinit()
181 if (ctlr->chip->cfg2 & VIACLK) in ata_via_chipinit()
185 if (ctlr->chip->cfg2 & VIABUG) in ata_via_chipinit()
214 if (ctlr->chip->cfg2 & VIABAR) { in ata_via_ch_attach()
271 if (ctlr->chip->cfg2 & VIABAR) { in ata_via_ch_detach()
320 if ((ctlr->chip->cfg2 & VIABAR) && (ch->unit > 1)) { in ata_via_new_setmode()
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H A Data-highpoint.c102 ctlr->chip = idx; in ata_highpoint_probe()
115 if (ctlr->chip->cfg2 == HPT_OLD) { in ata_highpoint_chipinit()
128 if (ctlr->chip->cfg1 < HPT_372) in ata_highpoint_chipinit()
151 if (ctlr->chip->cfg1 == HPT_366) in ata_highpoint_ch_attach()
182 mode = min(mode, ctlr->chip->max_dma); in ata_highpoint_setmode()
191 timings33[ata_mode2idx(mode)][ctlr->chip->cfg1], 4); in ata_highpoint_setmode()
203 if (ctlr->chip->cfg1 == HPT_374 && pci_get_function(parent) == 1) { in ata_highpoint_check_80pin()
H A Data-nvidia.c176 if (!(ctlr->chip = ata_match_chip(dev, ids))) in ata_nvidia_probe()
179 if ((ctlr->chip->cfg1 & NVAHCI) && in ata_nvidia_probe()
196 if (ctlr->chip->cfg1 & NVAHCI) { in ata_nvidia_chipinit()
199 } else if (ctlr->chip->max_dma >= ATA_SA150) { in ata_nvidia_chipinit()
207 int offset = ctlr->chip->cfg1 & NV4 ? 0x0440 : 0x0010; in ata_nvidia_chipinit()
217 if (ctlr->chip->cfg1 & NVQ) { in ata_nvidia_chipinit()
286 int offset = ctlr->chip->cfg1 & NV4 ? 0x0440 : 0x0010; in ata_nvidia_status()
287 int shift = ch->unit << (ctlr->chip->cfg1 & NVQ ? 4 : 2); in ata_nvidia_status()
291 if (ctlr->chip->cfg1 & NVQ) in ata_nvidia_status()
301 if (ctlr->chip->cfg1 & NVQ) in ata_nvidia_status()
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/freebsd-14.2/sys/contrib/device-tree/Bindings/mtd/
H A Dfsl-upm-nand.txt5 - reg : should specify localbus chip select and size used for the chip.
10 - fsl,upm-addr-line-cs-offsets : address offsets for multi-chip support.
11 The corresponding address lines are used to select the chip.
13 (R/B#). For multi-chip devices, "n" GPIO definitions are required
17 - fsl,upm-wait-flags : add chip-dependent short delays after running the
20 - chip-delay : chip dependent delay for transferring data from array to
24 Each flash chip described may optionally contain additional sub-nodes
55 /* Multi-chip NAND device */
/freebsd-14.2/contrib/ofed/libcxgb4/
H A Dt4_chip_type.h70 static inline int is_t4(enum chip_type chip) in is_t4() argument
72 return (CHELSIO_CHIP_VERSION(chip) == CHELSIO_T4); in is_t4()
75 static inline int is_t5(enum chip_type chip) in is_t5() argument
77 return (CHELSIO_CHIP_VERSION(chip) == CHELSIO_T5); in is_t5()
80 static inline int is_t6(enum chip_type chip) in is_t6() argument
82 return (CHELSIO_CHIP_VERSION(chip) == CHELSIO_T6); in is_t6()
/freebsd-14.2/sys/contrib/device-tree/Bindings/display/mediatek/
H A Dmediatek,disp.txt29 - compatible: "mediatek,<chip>-disp-<function>", one of
32 "mediatek,<chip>-disp-rdma" - read DMA / line buffer
33 "mediatek,<chip>-disp-wdma" - write DMA
35 "mediatek,<chip>-disp-color" - color processor
36 "mediatek,<chip>-disp-dither" - dither
38 "mediatek,<chip>-disp-gamma" - gamma correction
45 "mediatek,<chip>-disp-mutex" - display mutex
46 "mediatek,<chip>-disp-od" - overdrive
60 "mediatek,<chip>-disp-ovl"
61 "mediatek,<chip>-disp-rdma"
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/freebsd-14.2/sys/contrib/dev/rtw89/
H A Defuse.c24 if (rtwdev->chip->chip_id != RTL8852A) in rtw89_switch_efuse_bank()
53 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; in rtw89_enable_efuse_pwr_cut_ddv()
72 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; in rtw89_disable_efuse_pwr_cut_ddv()
195 u32 logical_size = rtwdev->chip->logical_efuse_size; in rtw89_dump_logical_efuse_map()
196 u8 sec_ctrl_size = rtwdev->chip->sec_ctrl_efuse_size; in rtw89_dump_logical_efuse_map()
236 u32 phy_size = rtwdev->chip->physical_efuse_size; in rtw89_parse_efuse_map()
237 u32 log_size = rtwdev->chip->logical_efuse_size; in rtw89_parse_efuse_map()
238 u32 dav_phy_size = rtwdev->chip->dav_phy_efuse_size; in rtw89_parse_efuse_map()
239 u32 dav_log_size = rtwdev->chip->dav_log_efuse_size; in rtw89_parse_efuse_map()
305 u32 phycap_addr = rtwdev->chip->phycap_addr; in rtw89_parse_phycap_map()
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/freebsd-14.2/sys/contrib/device-tree/Bindings/input/touchscreen/
H A Dpixcir_i2c_ts.txt5 - reg: I2C address of the chip
6 - interrupts: interrupt to which the chip is connected
7 - attb-gpio: GPIO connected to the ATTB line of the chip
12 - reset-gpios: GPIO connected to the RESET line of the chip
13 - enable-gpios: GPIO connected to the ENABLE line of the chip
14 - wake-gpios: GPIO connected to the WAKE line of the chip
H A Dmelfas_mip4.txt5 - reg: I2C slave address of the chip (0x48 or 0x34)
6 - interrupts: interrupt to which the chip is connected
9 - ce-gpios: GPIO connected to the CE (chip enable) pin of the chip
/freebsd-14.2/sys/contrib/device-tree/Bindings/net/nfc/
H A Dnfcmrvl.txt12 - reset-n-io: Output GPIO pin used to reset the chip (active low).
13 - hci-muxed: Specifies that the chip is muxing NCI over HCI frames.
15 Optional UART-based chip specific properties:
16 - flow-control: Specifies that the chip is using RTS/CTS.
17 - break-control: Specifies that the chip needs specific break management.
19 Optional I2C-based chip specific properties:
20 - i2c-int-falling: Specifies that the chip read event shall be trigged on
22 - i2c-int-rising: Specifies that the chip read event shall be trigged on
/freebsd-14.2/sys/contrib/device-tree/Bindings/power/reset/
H A Docelot-reset.txt11 - compatible: "mscc,ocelot-chip-reset", "mscc,luton-chip-reset",
12 "mscc,jaguar2-chip-reset" or "microchip,sparx5-chip-reset"
16 compatible = "mscc,ocelot-chip-reset";
H A Dltc2952-poweroff.txt3 This chip is used to externally trigger a system shut down. Once the trigger has
4 been sent, the chip's watchdog has to be reset to gracefully shut down.
11 chip's watchdog line
13 chip's kill line
17 chip's trigger line. If this property is not set, the
18 trigger function is ignored and the chip is kept alive
/freebsd-14.2/sys/contrib/device-tree/Bindings/spi/
H A Dspi-sprd-adi.txt4 analog chip (such as PMIC) from digital chip. ADI controller follows the SPI
9 48 hardware channels to access analog chip. For 2 software read/write channels,
10 users should set ADI registers to access analog chip. For hardware channels,
12 which means we can just link one analog chip address to one hardware channel,
13 then users can access the mapped analog chip address by this hardware channel
19 the analog chip address where user want to access by hardware components.
21 Since we have multi-subsystems will use unique ADI to access analog chip, when
36 - #address-cells: Number of cells required to define a chip select address
38 - #size-cells: Size of cells required to define a chip select address size
48 value specifies the analog chip address where user want to access
H A Dsprd,spi-adi.yaml16 analog chip (such as PMIC) from digital chip. ADI controller follows the SPI
21 48 hardware channels to access analog chip. For 2 software read/write channels,
22 users should set ADI registers to access analog chip. For hardware channels,
24 which means we can just link one analog chip address to one hardware channel,
25 then users can access the mapped analog chip address by this hardware channel
31 the analog chip address where user want to access by hardware components.
33 Since we have multi-subsystems will use unique ADI to access analog chip, when
76 - description: The analog chip address where user want to access by
/freebsd-14.2/sys/contrib/device-tree/Bindings/mips/cavium/
H A Dbootbus.txt3 The Octeon Boot Bus is a configurable parallel bus with 8 chip
4 selects. Each chip select is independently configurable.
13 - #address-cells: Must be <2>. The first cell is the chip select
14 within the bootbus. The second cell is the offset from the chip select.
19 parent-bus-address, length) for each active chip select. If the
20 length element for any triplet is zero, the chip select is disabled,
23 The configuration parameters for each chip select are stored in child
29 - cavium,cs-index: A single cell indicating the chip select that
60 the bus for this chip select.
72 /* The chip select number and offset */
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