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Searched refs:buildSelect (Results 1 – 8 of 8) sorted by relevance

/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPULegalizerInfo.cpp2290 B.buildSelect(Dst, CmpRes, BuildPtr, FlatNull); in legalizeAddrSpaceCast()
2372 auto Add = B.buildSelect(S64, And, One, Zero); in legalizeFceil()
3615 R = B.buildSelect(Ty, Underflow, Zero, R); in legalizeFExp()
3626 R = B.buildSelect(Ty, Overflow, Inf, R, Flags); in legalizeFExp()
4504 auto C3 = B.buildSelect(S32, CmpEq, C2, C1); in legalizeUnsignedDIV_REM64Impl()
4523 auto C6 = B.buildSelect( in legalizeUnsignedDIV_REM64Impl()
4538 auto Sel1 = B.buildSelect( in legalizeUnsignedDIV_REM64Impl()
4545 auto Sel2 = B.buildSelect( in legalizeUnsignedDIV_REM64Impl()
5015 Mant = B.buildSelect(Ty, IsFinite, Mant, Val); in legalizeFFREXP()
5044 auto Sel = B.buildSelect(S32, CmpRes, C1, C2, Flags); in legalizeFDIVFastIntrin()
[all …]
H A DAMDGPURegisterBankInfo.cpp144 B.buildSelect(DstReg, SrcReg, True, False); in applyBank()
1982 auto S = B.buildSelect(EltTy, Cmp, in foldExtractEltToCmpSelect()
2087 Register Select = B.buildSelect(EltTy, Cmp, Op0, Op1).getReg(0); in foldInsertEltToCmpSelect()
2357 B.buildSelect(DefRegs[0], CondRegs[0], Src1Regs[0], Src2Regs[0]); in applyMappingImpl()
2358 B.buildSelect(DefRegs[1], CondRegs[0], Src1Regs[1], Src2Regs[1]); in applyMappingImpl()
2775 B.buildSelect(DefRegs[0], SrcReg, True, False); in applyMappingImpl()
2778 auto Sel = B.buildSelect(SelType, SrcReg, True, False); in applyMappingImpl()
2782 B.buildSelect(DstReg, SrcReg, True, False); in applyMappingImpl()
/freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/
H A DLegalizerHelper.cpp5096 auto Hi = MIRBuilder.buildSelect( in narrowScalarShift()
5123 auto Lo = MIRBuilder.buildSelect( in narrowScalarShift()
5913 auto Select = MIRBuilder.buildSelect(NarrowTy, in narrowScalarSelect()
5919 auto Select = MIRBuilder.buildSelect( in narrowScalarSelect()
6577 MIRBuilder.buildSelect(Dst, Src, True, False); in lowerUITOFP()
6606 MIRBuilder.buildSelect(Dst, Src, True, False); in lowerSITOFP()
6673 MIRBuilder.buildSelect(Dst, FCMP, FPTOSI, Res); in lowerFPTOUI()
6840 V = MIRBuilder.buildSelect(S32, CmpEGt30, in lowerFPTRUNC_F64_TO_F16()
6905 MIRBuilder.buildSelect(Dst, Cmp, Src0, Src1); in lowerMinMax()
7620 MIRBuilder.buildSelect(Res, Ov, Clamp, Tmp); in lowerAddSubSatToAddoSubo()
[all …]
H A DMachineIRBuilder.cpp861 MachineIRBuilder::buildSelect(const DstOp &Res, const SrcOp &Tst, in buildSelect() function in MachineIRBuilder
H A DCombinerHelper.cpp3532 Builder.buildSelect(Dst, SelectCond, FoldTrue, FoldFalse, MI.getFlags()); in applyFoldBinOpIntoSelect()
5128 return MIB.buildSelect(Ty, IsOne, LHS, Q); in buildUDivUsingMul()
H A DIRTranslator.cpp1526 MIRBuilder.buildSelect(ResRegs[i], Tst, Op0Regs[i], Op1Regs[i], Flags); in translateSelect()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/SPIRV/
H A DSPIRVBuiltins.cpp317 return MIRBuilder.buildSelect(ReturnRegister, SourceRegister, TrueConst, in buildSelectInst()
1014 MIRBuilder.buildSelect(SelectionResult, CompareRegister, Extracted, in genWorkgroupQuery()
1407 MIRBuilder.buildSelect(Call->ReturnRegister, Call->Arguments[0], in generateSelectInst()
/freebsd-14.2/contrib/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/
H A DMachineIRBuilder.h1214 MachineInstrBuilder buildSelect(const DstOp &Res, const SrcOp &Tst,