Searched refs:buildSExtInReg (Results 1 – 6 of 6) sorted by relevance
| /freebsd-14.2/contrib/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/ |
| H A D | LegalizationArtifactCombiner.h | 208 Builder.buildSExtInReg(DstReg, TruncSrc, SizeInBits); in tryCombineSExt()
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| H A D | MachineIRBuilder.h | 681 MachineInstrBuilder buildSExtInReg(const DstOp &Res, const SrcOp &Op, int64_t ImmOp) { in buildSExtInReg() function
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPURegisterBankInfo.cpp | 1100 B.buildSExtInReg(MI.getOperand(0), WideLoad, MemSize); in applyMappingLoad()
1727 auto ExtLo = B.buildSExtInReg(S32, Bitcast, 16); in unpackV2S16ToS32()
2631 B.buildSExtInReg(DstRegs[0], Freeze, Amt); in applyMappingImpl()
2639 B.buildSExtInReg(DstRegs[1], DstRegs[0], Amt - 32); in applyMappingImpl()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/ |
| H A D | MachineIRBuilder.cpp | 516 return buildSExtInReg(Res, Op, 1); in buildBoolExtInReg()
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| H A D | LegalizerHelper.cpp | 2291 ExtResult = MIRBuilder.buildSExtInReg(WideTy, Mul, SrcBitWidth); in widenScalarMulo()
3331 MIRBuilder.buildSExtInReg(LoadReg, NewLoad, MemSizeInBits); in lowerLoad()
7978 MaskElt = MIRBuilder.buildSExtInReg(MaskTy, MaskElt, 1).getReg(0); in lowerSelect()
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| H A D | CombinerHelper.cpp | 3114 Builder.buildSExtInReg(MI.getOperand(0).getReg(), Src, Size - ShiftAmt); in applyAshShlToSextInreg()
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