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Searched refs:buildCopy (Results 1 – 25 of 31) sorted by relevance

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/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsCallLowering.cpp177 auto CopyLo = MIRBuilder.buildCopy(LLT::scalar(32), VALo.getLocReg()); in assignCustomValue()
178 auto CopyHi = MIRBuilder.buildCopy(LLT::scalar(32), VAHi.getLocReg()); in assignCustomValue()
224 MIRBuilder.buildCopy(PhysReg, ExtReg); in assignValueToReg()
237 auto SPReg = MIRBuilder.buildCopy(p0, Register(Mips::SP)); in getStackAddress()
283 MIRBuilder.buildCopy(VALo.getLocReg(), Lo); in assignCustomValue()
284 MIRBuilder.buildCopy(VAHi.getLocReg(), Hi); in assignCustomValue()
288 MIRBuilder.buildCopy(VALo.getLocReg(), Lo); in assignCustomValue()
289 MIRBuilder.buildCopy(VAHi.getLocReg(), Hi); in assignCustomValue()
430 MIRBuilder.buildCopy(RegTy, Register(ArgRegs[I])); in lowerFormalArguments()
537 MIRBuilder.buildCopy( in lowerCall()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86AvoidStoreForwardingBlocks.cpp109 void buildCopy(MachineInstr *LoadInst, unsigned NLoadOpcode, int64_t LoadDisp,
380 void X86AvoidSFBPass::buildCopy(MachineInstr *LoadInst, unsigned NLoadOpcode, in buildCopy() function in X86AvoidSFBPass
440 buildCopy(LoadInst, getYMMtoXMMLoadOpcode(LoadInst->getOpcode()), LdDisp, in buildCopies()
451 buildCopy(LoadInst, X86::MOV64rm, LdDisp, StoreInst, X86::MOV64mr, StDisp, in buildCopies()
461 buildCopy(LoadInst, X86::MOV32rm, LdDisp, StoreInst, X86::MOV32mr, StDisp, in buildCopies()
471 buildCopy(LoadInst, X86::MOV16rm, LdDisp, StoreInst, X86::MOV16mr, StDisp, in buildCopies()
481 buildCopy(LoadInst, X86::MOV8rm, LdDisp, StoreInst, X86::MOV8mr, StDisp, in buildCopies()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/M68k/GISel/
H A DM68kCallLowering.cpp63 MIRBuilder.buildCopy(PhysReg, ExtReg); in assignValueToReg()
83 auto SPReg = MIRBuilder.buildCopy(p0, StackReg).getReg(0); in getStackAddress()
186 MIRBuilder.buildCopy(ValVReg, PhysReg); in assignValueToReg()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMCallLowering.cpp102 auto SPReg = MIRBuilder.buildCopy(p0, Register(ARM::SP)); in getStackAddress()
121 MIRBuilder.buildCopy(PhysReg, ExtReg); in assignValueToReg()
298 MIRBuilder.buildCopy(ValVReg, PhysReg); in assignValueToReg()
305 auto PhysRegToVReg = MIRBuilder.buildCopy(LLT::scalar(LocSize), PhysReg); in assignValueToReg()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/X86/GISel/
H A DX86CallLowering.cpp98 MIRBuilder.buildCopy(p0, STI.getRegisterInfo()->getStackRegister()); in getStackAddress()
112 MIRBuilder.buildCopy(PhysReg, ExtReg); in assignValueToReg()
155 MIRBuilder.buildCopy(Is64Bit ? X86::RAX : X86::EAX, FLI.DemoteRegister); in lowerReturn()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUCallLowering.cpp93 MIRBuilder.buildCopy(PhysReg, ExtReg); in assignValueToReg()
127 auto Copy = MIRBuilder.buildCopy(LLT::scalar(32), PhysReg); in assignValueToReg()
215 SPReg = MIRBuilder.buildCopy(PtrTy, in getStackAddress()
237 MIRBuilder.buildCopy(PhysReg, ExtReg); in assignValueToReg()
490 B.buildCopy(VReg, InputPtrReg); in allocateHSAUserSGPRs()
1163 auto ScratchRSrcReg = MIRBuilder.buildCopy(LLT::fixed_vector(4, 32), in handleImplicitCallArguments()
1170 MIRBuilder.buildCopy(CalleeRSrcReg, ScratchRSrcReg); in handleImplicitCallArguments()
1175 MIRBuilder.buildCopy((Register)ArgReg.first, ArgReg.second); in handleImplicitCallArguments()
H A DAMDGPURegisterBankInfo.cpp717 Src = B.buildCopy(Ty, Src).getReg(0); in buildReadFirstLane()
886 OpReg = B.buildCopy(OpTy, OpReg).getReg(0); in executeInWaterfallLoop()
1204 auto SPCopy = B.buildCopy(PtrTy, SPReg); in applyMappingDynStackAlloc()
1595 Register VSrc0 = B.buildCopy(S32, Src0).getReg(0); in applyMappingMAD_64_32()
1596 Register VSrc1 = B.buildCopy(S32, Src1).getReg(0); in applyMappingMAD_64_32()
1645 DstLo = B.buildCopy(S32, DstLo).getReg(0); in applyMappingMAD_64_32()
1646 DstHi = B.buildCopy(S32, DstHi).getReg(0); in applyMappingMAD_64_32()
1694 B.buildCopy(Dst1, Carry); in applyMappingMAD_64_32()
1909 B.buildCopy(Hi32Reg, Lo32Reg); in extendLow32IntoHigh32()
1994 B.buildCopy(DstReg, Res[L]); in foldExtractEltToCmpSelect()
[all …]
H A DAMDGPURegBankCombiner.cpp144 Register VgprReg = B.buildCopy(MRI.getType(Reg), Reg).getReg(0); in getAsVgpr()
H A DAMDGPULegalizerInfo.cpp2279 B.buildCopy(Dst, BuildPtr); in legalizeAddrSpaceCast()
2647 B.buildCopy(Dst, Unmerge.getReg(IdxVal)); in legalizeExtractVectorElt()
3346 B.buildCopy(Dst, R); in legalizeFlogCommon()
3629 B.buildCopy(Dst, R); in legalizeFExp()
4171 B.buildCopy(DstReg, LiveIn); in loadInputValue()
5018 B.buildCopy(Res0, Mant); in legalizeFFREXP()
6649 B.buildCopy(SGPR01, Temp); in legalizeTrapHsaQueuePtr()
6664 B.buildCopy(SGPR01, LiveIn); in legalizeTrapHsaQueuePtr()
6893 auto TTMP8 = B.buildCopy(S32, Register(AMDGPU::TTMP8)); in legalizeWaveID()
/freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/
H A DInlineAsmLowering.cpp211 MIRBuilder.buildCopy(Dst, Src); in buildAnyextOrCopy()
577 MIRBuilder.buildCopy(Tmp1Reg, SrcReg); in lowerInlineAsm()
581 MIRBuilder.buildCopy(ResRegs[i], SrcReg); in lowerInlineAsm()
H A DIRTranslator.cpp346 MIRBuilder.buildCopy( in translateCompare()
349 MIRBuilder.buildCopy( in translateCompare()
1384 MIRBuilder.buildCopy(Regs[0], VReg); in translateLoad()
1433 MIRBuilder.buildCopy(VReg, Vals[0]); in translateStore()
1542 MIRBuilder.buildCopy(Regs[0], Src); in translateCopy()
1680 MIRBuilder.buildCopy(getOrCreateVReg(U), BaseReg); in translateGetElementPtr()
2305 MIRBuilder.buildCopy(getOrCreateVReg(CI), in translateKnownIntrinsic()
2511 MIRBuilder.buildCopy(SwiftInVReg, SwiftError.getOrCreateVRegUseAt( in translateCallBase()
2852 MIRBuilder.buildCopy(ResRegs[0], ExceptionReg); in translateLandingPad()
2860 MIRBuilder.buildCopy(PtrVReg, SelectorReg); in translateLandingPad()
H A DCSEMIRBuilder.cpp150 return buildCopy(Op.getReg(), MIB.getReg(0)); in generateCopiesIfRequired()
H A DCallLowering.cpp807 MIRBuilder.buildCopy(Args[i].Regs[0], StackAddr); in handleAssignments()
1275 MIRBuilder.buildCopy(ValVReg, PhysReg); in assignValueToReg()
1279 auto Copy = MIRBuilder.buildCopy(LocTy, PhysReg); in assignValueToReg()
H A DLegalizerHelper.cpp4841 MIRBuilder.buildCopy(DstReg, SplitSrcs[0]); in fewerElementsVectorReductions()
4850 MIRBuilder.buildCopy(DstReg, Acc); in fewerElementsVectorReductions()
4908 MIRBuilder.buildCopy(DstReg, Acc); in fewerElementsVectorSeqReductions()
5734 MIRBuilder.buildCopy(DstReg, DstRegs[0]); in narrowScalarExtract()
7232 MIRBuilder.buildCopy(DstReg, BuildVec[0]); in lowerShuffleVector()
7245 auto SPTmp = MIRBuilder.buildCopy(PtrTy, SPReg); in getDynStackAllocTargetPtr()
7278 MIRBuilder.buildCopy(SPReg, SPTmp); in lowerDynStackAlloc()
7279 MIRBuilder.buildCopy(Dst, SPTmp); in lowerDynStackAlloc()
7750 MIRBuilder.buildCopy(ValReg, PhysReg); in lowerReadWriteRegister()
7752 MIRBuilder.buildCopy(PhysReg, ValReg); in lowerReadWriteRegister()
[all …]
H A DMachineIRBuilder.cpp305 MachineInstrBuilder MachineIRBuilder::buildCopy(const DstOp &Res, in buildCopy() function in MachineIRBuilder
520 return buildCopy(Res, Op); in buildBoolExtInReg()
579 return buildCopy(Dst, Src); in buildCast()
H A DCombinerHelper.cpp168 Builder.buildCopy(ToReg, FromReg); in replaceRegWith()
392 Builder.buildCopy(NewDstReg, Ops[0]); in applyCombineShuffleVector()
426 Builder.buildCopy(DstReg, SrcReg); in applyShuffleToExtract()
868 Builder.buildCopy(MI.getOperand(0).getReg(), MI.getOperand(1).getReg()); in applySextTruncSextLoad()
2005 SrcReg = Builder.buildCopy(MRI.getType(SrcReg), SrcReg).getReg(0); in applyCombineUnmergeMergeToPlainValues()
2286 Builder.buildCopy(DstReg, Reg); in applyCombineI2PToP2I()
4943 B.buildCopy(Dst, LHS); in matchAddOBy0()
4999 MatchInfo = [=](MachineIRBuilder &B) { B.buildCopy(Dst, ReplaceReg); }; in matchSubAddSameReg()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/
H A DAArch64CallLowering.cpp265 SPReg = MIRBuilder.buildCopy(p0, Register(AArch64::SP)).getReg(0); in getStackAddress()
290 MIRBuilder.buildCopy(PhysReg, ExtReg); in assignValueToReg()
462 MIRBuilder.buildCopy(AArch64::X21, SwiftErrorVReg); in lowerReturn()
520 MIRBuilder.buildCopy(Register(F.VReg), Register(F.PReg)); in handleMustTailForwardedRegisters()
1177 MIRBuilder.buildCopy(ForwardedReg, Register(F.VReg)); in lowerTailCall()
1378 MIRBuilder.buildCopy(Info.SwiftErrorVReg, Register(AArch64::X21)); in lowerCall()
H A DAArch64InstructionSelector.cpp2700 MIB.buildCopy({DefReg}, {DefGPRReg}); in select()
3614 MIB.buildCopy(DstPtrCopy, DstPtr); in selectMOPS()
3615 MIB.buildCopy(SrcValCopy, SrcOrVal); in selectMOPS()
3616 MIB.buildCopy(SizeCopy, Size); in selectMOPS()
3876 MIB.buildCopy(DstReg, Cmp.getReg(0)); in selectVectorICmp()
5690 auto Copy = MIB.buildCopy(Dst, LdMI.getReg(1)); in selectIndexedExtLoad()
6693 MIB.buildCopy({SrcReg}, {I.getOperand(2)}); in selectIntrinsic()
6711 MIB.buildCopy({I.getOperand(0)}, {DstReg}); in selectIntrinsic()
6760 MIB.buildCopy({DstReg}, {FrameAddr}); in selectIntrinsic()
7525 auto Copy = MIB.buildCopy({&RC}, {Reg}); in moveScalarRegClass()
[all …]
H A DAArch64PostLegalizerCombiner.cpp244 B.buildCopy(DstReg, Res.getReg(0)); in matchAArch64MulConstCombine()
H A DAArch64PreLegalizerCombiner.cpp551 B.buildCopy(DstReg, outReg); in applyExtUaddvToUaddlv()
H A DAArch64LegalizerInfo.cpp1500 MIB.buildCopy(DstReg, ExtReg); in legalizeIntrinsic()
2074 MIRBuilder.buildCopy(Dst, SPTmp); in legalizeDynStackAlloc()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/PowerPC/GISel/
H A DPPCCallLowering.cpp55 MIRBuilder.buildCopy(PhysReg, ExtReg); in assignValueToReg()
/freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/
H A DSplitKit.h432 SlotIndex buildCopy(Register FromReg, Register ToReg, LaneBitmask LaneMask,
H A DSplitKit.cpp547 SlotIndex SplitEditor::buildCopy(Register FromReg, Register ToReg, in buildCopy() function in SplitEditor
638 Def = buildCopy(Edit->getReg(), Reg, LaneMask, MBB, I, Late, RegIdx); in defFromParent()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/RISCV/GISel/
H A DRISCVCallLowering.cpp75 SPReg = MIRBuilder.buildCopy(p0, Register(RISCV::X2)).getReg(0); in getStackAddress()
107 MIRBuilder.buildCopy(PhysReg, ExtReg); in assignValueToReg()

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