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Searched refs:buildBitcast (Results 1 – 9 of 9) sorted by relevance

/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUPreLegalizerCombiner.cpp203 auto Bitcast = B.buildBitcast({S32}, CvtPk); in applyClampI64ToI16()
H A DAMDGPULegalizerInfo.cpp530 auto Scalar = B.buildBitcast(ScalarTy, BitcastReg); in castBufferRsrcFromV4I32()
558 return B.buildBitcast(VectorTy, Scalar).getReg(0); in castBufferRsrcToV4I32()
3756 B.buildBitcast(Dst, Merge); in legalizeBuildVector()
5535 Reg = B.buildBitcast(S32, Reg).getReg(0); in handleD16VData()
5554 Reg = B.buildBitcast(LLT::fixed_vector(2, S32), Reg).getReg(0); in handleD16VData()
6040 AddrReg = B.buildBitcast(V2S16, AddrReg).getReg(0); in packImage16bitOpsToDwords()
6432 B.buildBitcast(DstReg, ResultRegs[0]); in legalizeImageIntrinsic()
6446 Reg = B.buildBitcast(V2S16, Reg).getReg(0); in legalizeImageIntrinsic()
6775 {B.buildBitcast( in legalizeBVHIntrinsic()
6779 B.buildBitcast( in legalizeBVHIntrinsic()
[all …]
H A DAMDGPURegisterBankInfo.cpp1724 auto Bitcast = B.buildBitcast(S32, Src); in unpackV2S16ToS32()
2100 B.buildBitcast(MI.getOperand(0).getReg(), Vec); in foldInsertEltToCmpSelect()
2864 auto CastSrc = B.buildBitcast(Vec32, SrcReg); in applyMappingImpl()
2979 auto CastSrc = B.buildBitcast(Vec32, SrcReg); in applyMappingImpl()
3014 B.buildBitcast(DstReg, InsHi); in applyMappingImpl()
3031 B.buildBitcast(DstReg, InsHi); in applyMappingImpl()
H A DAMDGPUCallLowering.cpp83 ExtReg = MIRBuilder.buildBitcast(S32, ExtReg).getReg(0); in assignValueToReg()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/SPIRV/
H A DSPIRVPreLegalizer.cpp135 MIB.buildBitcast(MI.getOperand(0).getReg(), MI.getOperand(2).getReg()); in insertBitcasts()
152 MIB.buildBitcast(Def, Source); in insertBitcasts()
/freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/
H A DCallLowering.cpp357 B.buildBitcast(OrigRegs[0], Regs[0]); in buildCopyFromRegs()
420 CastRegs[0] = B.buildBitcast(NewTy, Regs[0]).getReg(0); in buildCopyFromRegs()
434 CastRegs[I++] = B.buildBitcast(GCDTy, SrcReg).getReg(0); in buildCopyFromRegs()
H A DLegalizerHelper.cpp1715 return MIRBuilder.buildBitcast(NewTy, NewVal).getReg(0); in coerceToScalar()
1769 Op.setReg(MIRBuilder.buildBitcast(CastTy, Op).getReg(0)); in bitcastSrc()
1776 MIRBuilder.buildBitcast(MO, CastDst); in bitcastDst()
3053 SrcReg = MIRBuilder.buildBitcast(DstCastTy, SrcReg).getReg(0); in lowerBitcast()
3114 Register CastVec = MIRBuilder.buildBitcast(CastTy, SrcVec).getReg(0); in bitcastExtractVectorElt()
3150 MIRBuilder.buildBitcast(Dst, NewVec); in bitcastExtractVectorElt()
3255 Register CastVec = MIRBuilder.buildBitcast(CastTy, SrcVec).getReg(0); in bitcastInsertVectorElt()
3289 MIRBuilder.buildBitcast(Dst, InsertedElt); in bitcastInsertVectorElt()
7344 SrcReg = MIRBuilder.buildBitcast(SrcIntTy, SrcReg).getReg(0); in lowerExtract()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/
H A DAArch64LegalizerInfo.cpp1667 auto Bitcast = MIRBuilder.buildBitcast(NewTy, ValReg); in legalizeLoadStore()
1671 MIRBuilder.buildBitcast(ValReg, NewLoad); in legalizeLoadStore()
1796 Val = MIRBuilder.buildBitcast(VTy, Val).getReg(0); in legalizeCTPOP()
/freebsd-14.2/contrib/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/
H A DMachineIRBuilder.h702 MachineInstrBuilder buildBitcast(const DstOp &Dst, const SrcOp &Src) { in buildBitcast() function