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Searched refs:buildAnyExt (Results 1 – 11 of 11) sorted by relevance

/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsLegalizerInfo.cpp376 Val = MIRBuilder.buildAnyExt(s32, Val).getReg(0); in legalizeCustom()
378 Val = MIRBuilder.buildAnyExt(s64, Val).getReg(0); in legalizeCustom()
/freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/
H A DCallLowering.cpp506 BVRegs.push_back(B.buildAnyExt(PartLLT, Unmerge.getReg(K)).getReg(0)); in buildCopyFromRegs()
546 B.buildAnyExt(DstRegs[i], UnmergeToEltTy.getReg(i)); in buildCopyToRegs()
1208 auto MIB = MIRBuilder.buildAnyExt(LocTy, ValReg); in extendRegister()
H A DInlineAsmLowering.cpp208 Src = MIRBuilder.buildAnyExt(LLT::scalar(DstSize), Src).getReg(0); in buildAnyextOrCopy()
H A DLegalizerHelper.cpp1204 MIRBuilder.buildAnyExt(DstReg, ImplicitReg); in narrowScalar()
1323 MIRBuilder.buildAnyExt(DstReg, TmpReg); in narrowScalar()
1936 SrcReg = MIRBuilder.buildAnyExt(WideTy, SrcReg).getReg(0); in widenScalarUnmergeValues()
1965 WideSrc = MIRBuilder.buildAnyExt(LCMTy, WideSrc).getReg(0); in widenScalarUnmergeValues()
2067 Src = MIRBuilder.buildAnyExt(WideTy, Src); in widenScalarExtract()
2223 auto LHS = MIRBuilder.buildAnyExt(WideTy, MI.getOperand(1)); in widenScalarAddSubShlSat()
2225 : MIRBuilder.buildAnyExt(WideTy, MI.getOperand(2)); in widenScalarAddSubShlSat()
3462 SrcReg = MIRBuilder.buildAnyExt(WideTy, SrcReg).getReg(0); in lowerStore()
5774 MIRBuilder.buildAnyExt(SrcReg, SrcRegs[I]); in narrowScalarInsert()
H A DMachineIRBuilder.cpp475 MachineInstrBuilder MachineIRBuilder::buildAnyExt(const DstOp &Res, in buildAnyExt() function in MachineIRBuilder
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUPostLegalizerCombiner.cpp375 CvtSrc = B.buildAnyExt(S32, CvtSrc).getReg(0); in applyCvtF32UByteN()
H A DAMDGPULegalizerInfo.cpp3900 Tmp = B.buildAnyExt(S64, LocalAccum[0]).getReg(0); in buildMultiply()
5386 auto ExtStride = B.buildAnyExt(S32, Stride); in legalizePointerAsRsrcIntrin()
5524 WideRegs.push_back(B.buildAnyExt(S32, Unmerge.getReg(I)).getReg(0)); in handleD16VData()
5586 Register AnyExt = B.buildAnyExt(LLT::scalar(32), VData).getReg(0); in fixStoreSourceType()
7200 MI.getOperand(5).setReg(B.buildAnyExt(S32, Index).getReg(0)); in legalizeIntrinsic()
7209 MI.getOperand(7).setReg(B.buildAnyExt(S32, Index).getReg(0)); in legalizeIntrinsic()
H A DAMDGPUCallLowering.cpp39 return Handler.MIRBuilder.buildAnyExt(LLT::scalar(32), ValVReg).getReg(0); in extendRegisterMin32()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/RISCV/GISel/
H A DRISCVCallLowering.cpp104 ValVReg = MIRBuilder.buildAnyExt(LLT::scalar(64), ValVReg).getReg(0); in assignValueToReg()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/
H A DAArch64LegalizerInfo.cpp1404 Register ExtValueReg = MIB.buildAnyExt(LLT::scalar(64), Value).getReg(0); in legalizeIntrinsic()
1962 MIRBuilder.buildAnyExt(LLT::scalar(64), Value).getReg(0); in legalizeMemOps()
/freebsd-14.2/contrib/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/
H A DMachineIRBuilder.h664 MachineInstrBuilder buildAnyExt(const DstOp &Res, const SrcOp &Op);