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Searched refs:bitsLT (Results 1 – 25 of 27) sorted by relevance

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/freebsd-14.2/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DValueTypes.h283 bool bitsLT(EVT VT) const { in bitsLT() function
H A DMachineValueType.h414 bool bitsLT(MVT VT) const { in bitsLT() function
H A DTargetLowering.h4664 return VT.bitsLT(MinVT) ? MinVT : VT; in getTypeForExtReturn()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMSelectionDAGInfo.cpp106 else if (Src.getValueType().bitsLT(MVT::i32)) in EmitSpecializedLibcall()
/freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/
H A DTargetLoweringBase.cpp1192 if (EVT(DestVT).bitsLT(NewVT)) // Value is expanded, e.g. i64 -> i16. in getVectorTypeBreakdownMVT()
1674 if (EVT(DestVT).bitsLT(NewVT)) { // Value is expanded, e.g. i64 -> i16. in getVectorTypeBreakdown()
1742 if (VT.bitsLT(MinVT)) in GetReturnInfo()
H A DCodeGenPrepare.cpp1482 if (SrcVT.bitsLT(DstVT)) in OptimizeNoopCopyExpression()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DR600ISelLowering.cpp1207 if (MemVT.bitsLT(MVT::i32)) in LowerSTORE()
1325 ExtType != ISD::NON_EXTLOAD && MemVT.bitsLT(MVT::i32)) { in LowerLOAD()
1551 if (VT.bitsLT(MVT::i32)) in allowsMisalignedMemoryAccesses()
H A DSIISelLowering.cpp1964 VT.bitsLT(MemVT)) { in convertArgType()
2941 if (VT.isScalarInteger() && VT.bitsLT(NewArg.getSimpleValueType())) in LowerFormalArguments()
6011 if (NewVT.bitsLT(MVT::i32)) { in ReplaceNodeResults()
9966 if (VT.bitsLT(Op.getValueType())) in getLoadExtOrTrunc()
/freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DSelectionDAG.cpp1581 if (VT.bitsLT(Op.getValueType())) in getVPZExtOrTrunc()
2963 if (LegalSVT.bitsLT(SVT)) in getSplatValue()
5771 if (N1.getOperand(0).getValueType().getScalarType().bitsLT( in getNode()
6362 if (LegalSVT.bitsLT(VT.getScalarType())) in FoldConstantArithmetic()
7845 if (VT.bitsLT(LargestVT)) { in getMemsetStores()
8510 assert(MemVT.getScalarType().bitsLT(VT.getScalarType()) && in getLoad()
8683 assert(SVT.getScalarType().bitsLT(VT.getScalarType()) && in getTruncStore()
8935 assert(SVT.getScalarType().bitsLT(VT.getScalarType()) && in getTruncStoreVP()
9187 assert(SVT.getScalarType().bitsLT(VT.getScalarType()) && in getTruncStridedStoreVP()
9952 assert(Ops[1].getValueType().bitsLT(VTList.VTs[0]) && in getNode()
[all …]
H A DLegalizeTypesGeneric.cpp224 assert(OldEltVT.bitsLT(OldVT) && "Result type smaller then element type!"); in ExpandRes_EXTRACT_VECTOR_ELT()
H A DLegalizeDAG.cpp1522 MemVT.bitsLT(Node->getOperand(0).getValueType()); in ExpandVectorBuildThroughStack()
1773 (SlotVT.bitsLT(DestVT) && in EmitStackConvert()
1803 assert(SlotVT.bitsLT(DestVT) && "Unknown extension!"); in EmitStackConvert()
3419 if (NewEltVT.bitsLT(EltVT)) { in ExpandNode()
5450 assert(NewEltVT.bitsLT(EltVT) && "not handled"); in PromoteNode()
5496 assert(NewEltVT.bitsLT(EltVT) && "not handled"); in PromoteNode()
H A DFastISel.cpp392 if (IdxVT.bitsLT(PtrVT)) { in getRegForGEPIndex()
1866 if (DstVT.bitsLT(SrcVT)) in selectOperator()
H A DSelectionDAGBuilder.cpp262 ValueVT.bitsLT(PartEVT)) { in getCopyFromParts()
275 if (ValueVT.bitsLT(PartEVT)) { in getCopyFromParts()
289 if (ValueVT.bitsLT(Val.getValueType())) { in getCopyFromParts()
310 ValueVT.bitsLT(PartEVT)) { in getCopyFromParts()
457 } else if (ValueVT.bitsLT(PartEVT)) { in getCopyFromPartsVector()
480 assert(ValueSVT.bitsLT(PartEVT) && "Unexpected types"); in getCopyFromPartsVector()
7600 if (CountVT.bitsLT(VT)) { in visitIntrinsicCall()
H A DDAGCombiner.cpp6476 if (LdStMemVT.bitsLT(MemVT)) in isLegalNarrowLdSt()
13708 if (SrcVT.bitsLT(VT) && VT.isVector()) { in visitZERO_EXTEND()
14122 if (AssertVT.bitsLT(BigA_AssertVT)) { in visitAssertExt()
14433 ExtVT.bitsLT(cast<VTSDNode>(N0.getOperand(1))->getVT())) in visitSIGN_EXTEND_INREG()
14689 if (N0.getOperand(0).getValueType().bitsLT(VT)) in visitTRUNCATE()
14706 if (ExtVT.bitsLT(VT) && TLI.preferSextInRegOfTruncate(VT, SrcVT, ExtVT)) { in visitTRUNCATE()
17652 if (VT.bitsLT(In.getValueType())) in visitFP_EXTEND()
21977 if (ResultVT.bitsLT(VecEltVT)) in scalarizeExtractedVectorLoad()
22405 if (ScalarVT.bitsLT(LVT) && !TLI.isTruncateFree(LVT, ScalarVT)) in visitEXTRACT_VECTOR_ELT()
24795 SVT = (SVT.bitsLT(Op.getValueType()) ? Op.getValueType() : SVT); in combineShuffleOfScalars()
[all …]
H A DLegalizeVectorTypes.cpp548 if (BoolVT.bitsLT(CondVT)) in ScalarizeVecRes_VSELECT()
3016 if (N->getValueType(0).bitsLT( in SplitVectorOperand()
3404 if (N->getValueType(0).bitsLT(EltVT)) { in SplitVecOp_EXTRACT_VECTOR_ELT()
H A DTargetLowering.cpp4796 else if (Op0.getValueType().bitsLT(VT)) in SimplifySetCC()
9903 if (VT.bitsLT(MVT::i32)) { in lowerCmpEqZeroToCtlzSrl()
10604 if (RType.bitsLT(Overflow.getValueType())) in expandMULO()
H A DLegalizeIntegerTypes.cpp5698 if (OpVT.bitsLT(NOutVTElem)) { in PromoteIntRes_BUILD_VECTOR()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMips64InstrInfo.td71 return cast<VTSDNode>(N->getOperand(1))->getVT().bitsLT(MVT::i32);
H A DMipsISelLowering.cpp4042 return VT.bitsLT(MinVT) ? MinVT : VT; in getTypeForExtReturn()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86ISelLoweringCall.cpp994 return VT.bitsLT(MinVT) ? MinVT : VT; in getTypeForExtReturn()
H A DX86FastISel.cpp3682 if (DstVT.bitsLT(SrcVT)) in fastSelectInstruction()
H A DX86ISelLowering.cpp21723 if (Sign.getSimpleValueType().bitsLT(VT)) in LowerFCOPYSIGN()
54294 if (OutVT16.bitsLT(In0.getValueType())) { in matchPMADDWD_2()
54298 if (OutVT16.bitsLT(In1.getValueType())) { in matchPMADDWD_2()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.cpp5196 if (IntVT.bitsLT(VT)) in lowerCTLZ_CTTZ_ZERO_UNDEF()
7718 assert(DstEltVT.bitsLT(SrcEltVT) && isPowerOf2_64(DstEltVT.getSizeInBits()) && in lowerVectorTruncLike()
8262 if (OpVT.bitsLT(XLenVT)) { in lowerVectorIntrinsicScalars()
11985 if (VT.bitsLT(XLenVT)) { in ReplaceNodeResults()
12893 if (ResultVT.bitsLT(VT.getVectorElementType())) { in narrowIndex()
15036 if (IndexVT.getVectorElementType().bitsLT(XLenVT)) { in legalizeScatterGatherIndexType()
15972 if (M1VT.bitsLT(VT)) { in PerformDAGCombine()
15997 if (M1VT.bitsLT(VecVT)) { in PerformDAGCombine()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64FastISel.cpp4952 if (IdxVT.bitsLT(PtrVT)) { in getRegForGEPIndex()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/LoongArch/
H A DLoongArchISelLowering.cpp677 dyn_cast<VTSDNode>(Op0.getOperand(1))->getVT().bitsLT(MVT::i32)) in lowerUINT_TO_FP()

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