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Searched refs:bitsLE (Results 1 – 19 of 19) sorted by relevance

/freebsd-14.2/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DValueTypes.h291 bool bitsLE(EVT VT) const { in bitsLE() function
H A DMachineValueType.h421 bool bitsLE(MVT VT) const { in bitsLE() function
H A DSelectionDAG.h848 VT.getVectorElementType().bitsLE(Op.getValueType()))) &&
864 VT.getVectorElementType().bitsLE(Op.getValueType()))) &&
/freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeFloatTypes.cpp1748 assert(LD->getMemoryVT().bitsLE(NVT) && "Float type not round?"); in ExpandFloatRes_LOAD()
1785 if (SrcVT.bitsLE(MVT::i32)) { in ExpandFloatRes_XINT_TO_FP()
1797 if (SrcVT.bitsLE(MVT::i64)) { in ExpandFloatRes_XINT_TO_FP()
1801 } else if (SrcVT.bitsLE(MVT::i128)) { in ExpandFloatRes_XINT_TO_FP()
1817 if (isSigned || SrcVT.bitsLE(MVT::i32)) { in ExpandFloatRes_XINT_TO_FP()
2108 assert(ST->getMemoryVT().bitsLE(NVT) && "Float type not round?"); in ExpandFloatOp_STORE()
H A DLegalizeIntegerTypes.cpp828 assert(Res.getValueType().bitsLE(NVT) && "Extension doesn't make sense!"); in PromoteIntRes_INT_EXTEND()
3498 if (Op.getValueType().bitsLE(NVT)) { in ExpandIntRes_ANY_EXTEND()
3883 if (N->getMemoryVT().bitsLE(NVT)) { in ExpandIntRes_LOAD()
4651 if (Op.getValueType().bitsLE(NVT)) { in ExpandIntRes_SIGN_EXTEND()
4683 if (EVT.bitsLE(Lo.getValueType())) { in ExpandIntRes_SIGN_EXTEND_INREG()
4972 if (Op.getValueType().bitsLE(NVT)) { in ExpandIntRes_ZERO_EXTEND()
5437 if (N->getMemoryVT().bitsLE(NVT)) { in ExpandIntOp_STORE()
5598 assert(PromEltVT.bitsLE(NOutVTElem) && in PromoteIntRes_EXTRACT_SUBVECTOR()
H A DLegalizeVectorOps.cpp1236 if (SrcVT.bitsLE(VT)) { in ExpandANY_EXTEND_VECTOR_INREG()
1295 if (SrcVT.bitsLE(VT)) { in ExpandZERO_EXTEND_VECTOR_INREG()
H A DSelectionDAG.cpp1140 EltVT.bitsLE(Op.getValueType()))) && in VerifySDNode()
1515 if (VT.bitsLE(Op.getValueType())) in getBoolExtOrTrunc()
1532 assert(VT.bitsLE(OpVT) && "Not extending!"); in getZeroExtendInReg()
5788 assert(N1.getValueType().bitsLE(VT) && in getNode()
5828 VT.getVectorElementType().bitsLE(N1.getValueType()))) && in getNode()
6741 VT.bitsLE(N1.getValueType()) && in getNode()
6755 assert(EVT.bitsLE(VT.getScalarType()) && "Not extending!"); in getNode()
6770 assert(EVT.bitsLE(VT) && "Not extending!"); in getNode()
6821 assert(cast<VTSDNode>(N2)->getVT().bitsLE(VT.getScalarType()) && in getNode()
H A DLegalizeDAG.cpp2633 (DestVT.bitsLE(MVT::f64) || in ExpandLegalINT_TO_FP()
5415 assert(NewEltVT.bitsLE(EltVT) && "not handled"); in PromoteNode()
H A DTargetLowering.cpp4727 isTypeLegal(VT) && VT.bitsLE(N0.getValueType()) && in SimplifySetCC()
5038 (VT == ShValTy || (isTypeLegal(VT) && VT.bitsLE(ShValTy))) && in SimplifySetCC()
H A DDAGCombiner.cpp6573 if (ExtVT.bitsLE(Load->getMemoryVT())) in SearchForAndLoads()
14855 if (LN0->isSimple() && LN0->getMemoryVT().bitsLE(VT)) { in visitTRUNCATE()
23907 MinVT = (!FoundMinVT || OpSVT.bitsLE(MinVT)) ? OpSVT : MinVT; in visitCONCAT_VECTORS()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.cpp3704 assert((ViaIntVT.bitsLE(XLenVT) || in lowerBuildVectorOfConstants()
3707 if (ViaIntVT.bitsLE(XLenVT) || isInt<32>(SplatValue)) { in lowerBuildVectorOfConstants()
4010 if (Scalar.getValueType().bitsLE(XLenVT)) { in lowerScalarSplat()
4058 if (ExtractedContainerVT.bitsLE(VT)) in lowerScalarInsert()
4073 if (!Scalar.getValueType().bitsLE(XLenVT)) in lowerScalarInsert()
8598 if (Scalar.getValueType().bitsLE(XLenVT)) { in LowerINTRINSIC_WO_CHAIN()
9191 auto InnerVT = VecVT.bitsLE(M1VT) ? VecVT : M1VT; in lowerReductionSeq()
10011 getLMUL1VT(ContainerVT).bitsLE(ContainerVT)) { in lowerFixedLengthVectorLoadToRVV()
10072 getLMUL1VT(ContainerVT).bitsLE(ContainerVT)) in lowerFixedLengthVectorStoreToRVV()
15803 MemVT.getVectorElementType().bitsLE(Subtarget.getXLenVT()) && in PerformDAGCombine()
[all …]
H A DRISCVInstrInfo.td1186 return cast<VTSDNode>(N->getOperand(1))->getVT().bitsLE(MVT::i32);
1191 return cast<VTSDNode>(N->getOperand(1))->getVT().bitsLE(MVT::i32);
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DR600ISelLowering.cpp1155 assert(VT.bitsLE(MVT::i32)); in LowerSTORE()
H A DAMDGPUISelLowering.cpp4263 if (Subtarget->has16BitInsts() && VT.getScalarType().bitsLE(MVT::i16)) in performMulCombine()
H A DSIISelLowering.cpp1856 VT.getScalarType().bitsLE(MVT::i16)) in getPreferredVectorAction()
6254 return Op.getValueType().bitsLE(VT) ? in getFPExtOrFPRound()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/M68k/
H A DM68kISelLowering.cpp1532 return VT.bitsLE(MVT::i32) || Subtarget.atLeastM68020(); in decomposeMulByConstant()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/LoongArch/
H A DLoongArchISelLowering.cpp702 dyn_cast<VTSDNode>(Op0.getOperand(1))->getVT().bitsLE(MVT::i32)) in lowerSINT_TO_FP()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMISelLowering.cpp17109 AVT.bitsLE(Ty); in PerformVECREDUCE_ADDCombine()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86ISelLowering.cpp25128 assert(MaskVT.bitsLE(Mask.getSimpleValueType()) && "Unexpected mask size!"); in getMaskNode()