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Searched refs:bitsGT (Results 1 – 23 of 23) sorted by relevance

/freebsd-14.2/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DValueTypes.h267 bool bitsGT(EVT VT) const { in bitsGT() function
H A DMachineValueType.h400 bool bitsGT(MVT VT) const { in bitsGT() function
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86SelectionDAGInfo.cpp106 if (AVT.bitsGT(MVT::i8)) { in EmitTargetCodeForMemset()
H A DX86FastISel.cpp3680 if (DstVT.bitsGT(SrcVT)) in fastSelectInstruction()
H A DX86ISelLowering.cpp21727 if (Sign.getSimpleValueType().bitsGT(VT)) in LowerFCOPYSIGN()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMSelectionDAGInfo.cpp104 if (Src.getValueType().bitsGT(MVT::i32)) in EmitSpecializedLibcall()
H A DARMISelLowering.cpp12799 unsigned ExtOp = VT.bitsGT(tmp.getValueType()) ? ISD::ANY_EXTEND : ISD::TRUNCATE; in AddCombineBUILD_VECTORToVPADDL()
/freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DFastISel.cpp394 } else if (IdxVT.bitsGT(PtrVT)) { in getRegForGEPIndex()
1864 if (DstVT.bitsGT(SrcVT)) in selectOperator()
H A DSelectionDAG.cpp1430 return VT.bitsGT(Op.getValueType()) in getFPExtendOrRound()
1442 VT.bitsGT(Op.getValueType()) in getStrictFPExtendOrRound()
1451 return VT.bitsGT(Op.getValueType()) ? in getAnyExtOrTrunc()
1457 return VT.bitsGT(Op.getValueType()) ? in getSExtOrTrunc()
1463 return VT.bitsGT(Op.getValueType()) ? in getZExtOrTrunc()
1579 if (VT.bitsGT(Op.getValueType())) in getVPZExtOrTrunc()
5540 if (SVT.bitsGT(VT.getScalarType())) { in foldCONCAT_VECTORS()
5765 assert(N1.getValueType().bitsGT(VT) && "Invalid truncate node, src < dst!"); in getNode()
5774 if (N1.getOperand(0).getValueType().bitsGT(VT)) in getNode()
6392 if (ScalarVT.isInteger() && ScalarVT.bitsGT(InSVT)) { in FoldConstantArithmetic()
[all …]
H A DDAGCombiner.cpp6437 if (!LoadedVT.bitsGT(ExtVT) || !ExtVT.isRound()) in isAndLoadExtLoad()
10960 EVT MaxVT = VT0.bitsGT(VT1) ? VT0 : VT1; in foldABSToABD()
14692 if (N0.getOperand(0).getValueType().bitsGT(VT)) in visitTRUNCATE()
21926 ResultVT.bitsGT(VecEltVT) ? ISD::NON_EXTLOAD : ISD::EXTLOAD; in scalarizeExtractedVectorLoad()
21960 if (ResultVT.bitsGT(VecEltVT)) { in scalarizeExtractedVectorLoad()
22217 if (InOp.getValueType().bitsGT(ScalarVT)) in visitEXTRACT_VECTOR_ELT()
22414 if (!BCVT.isVector() || ExtVT.bitsGT(BCVT.getVectorElementType())) in visitEXTRACT_VECTOR_ELT()
27082 if (XType.bitsGT(AType)) { in foldSelectCCToShiftAnd()
27102 if (XType.bitsGT(AType)) { in foldSelectCCToShiftAnd()
H A DLegalizeDAG.cpp1771 if ((SrcVT.bitsGT(SlotVT) && in EmitStackConvert()
1791 if (SrcVT.bitsGT(SlotVT)) in EmitStackConvert()
H A DLegalizeVectorTypes.cpp1800 if (EltVT.bitsGT(Elt.getValueType())) in SplitVecRes_INSERT_VECTOR_ELT()
2482 if (Ops[I].getValueType().bitsGT(EltVT)) in SplitVecRes_VECTOR_SHUFFLE()
H A DTargetLowering.cpp226 if (VT.bitsGT(LVT)) in findOptimalMemOpLowering()
4792 if (Op0.getValueType().bitsGT(VT)) in SimplifySetCC()
H A DSelectionDAGBuilder.cpp784 if (BuiltVectorTy.getVectorElementType().bitsGT( in getCopyToPartsVector()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DR600ISelLowering.cpp1558 return VT.bitsGT(MVT::i32) && Alignment >= Align(4); in allowsMisalignedMemoryAccesses()
1803 InVal = OpVT.bitsGT(InVal.getValueType()) ? in PerformDAGCombine()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVTargetTransformInfo.cpp307 if (IndexVT.getScalarType().bitsGT(ST.getXLenVT())) in getVRGatherIndexType()
H A DRISCVISelLowering.cpp4794 if (SVT.isInteger() && SVT.bitsGT(XLenVT)) { in lowerVECTOR_SHUFFLE()
5021 if (IndexVT.getScalarType().bitsGT(XLenVT)) { in lowerVECTOR_SHUFFLE()
5029 if (IndexVT.getScalarType().bitsGT(MVT::i16) && isUInt<16>(NumElts - 1) && in lowerVECTOR_SHUFFLE()
5160 if (FloatVT.bitsGT(VT)) { in lowerCTLZ_CTTZ_ZERO_UNDEF()
5198 else if (IntVT.bitsGT(VT)) in lowerCTLZ_CTTZ_ZERO_UNDEF()
7895 if (!SmallerVT.isValid() || !VecVT.bitsGT(SmallerVT)) in getSmallestVTForIndex()
7950 if (MinVLen == MaxVLen && ContainerVT.bitsGT(M1VT)) { in lowerINSERT_VECTOR_ELT()
8205 if (ContainerVT.bitsGT(LMUL2VT) && VecVT.isFixedLengthVector()) in lowerEXTRACT_VECTOR_ELT()
9477 if (VecVT.bitsGT(getLMUL1VT(VecVT))) { in lowerINSERT_SUBVECTOR()
9511 if (VecVT.bitsGT(InterSubVT)) in lowerINSERT_SUBVECTOR()
[all …]
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonISelLowering.cpp3471 if (Elem0.getValueType().bitsGT(TruncTy)) in PerformDAGCombine()
3512 if (ty(Elem0).bitsGT(TruncTy)) in PerformDAGCombine()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64TargetTransformInfo.cpp2547 EVT WiderTy = SrcTy.bitsGT(DstTy) ? SrcTy : DstTy; in getCastInstrCost()
H A DAArch64FastISel.cpp4954 } else if (IdxVT.bitsGT(PtrVT)) in getRegForGEPIndex()
H A DAArch64ISelLowering.cpp4858 if (InVT.bitsGT(VT)) in getSVEPredicateBitCast()
26520 if (VT.bitsGT(SrcVT)) { in LowerFixedLengthFPToIntToSVE()
/freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/
H A DCodeGenPrepare.cpp6825 if (!LoadResultVT.bitsGT(TruncVT) || !TruncVT.isRound() || in optimizeLoadExt()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp15681 if (Op1VT.bitsGT(mVT)) { in PerformDAGCombine()