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/freebsd-14.2/sys/dev/rtwn/
H A Dif_rtwnvar.h457 (((_sc)->sc_get_qmap)((_sc)))
494 (((_sc)->sc_power_on)((_sc)))
496 (((_sc)->sc_power_off)((_sc)))
504 (((_sc)->sc_llt_init)((_sc)))
508 (((_sc)->sc_lc_calib)((_sc)))
510 (((_sc)->sc_iq_calib)((_sc)))
547 (((_sc)->sc_set_rssi)((_sc)))
568 (((_sc)->sc_temp_read)((_sc)))
574 (((_sc)->sc_init_intr)((_sc)))
580 (((_sc)->sc_init_bb)((_sc)))
[all …]
/freebsd-14.2/sys/dev/wpi/
H A Dif_wpivar.h259 #define WPI_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx) argument
260 #define WPI_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx) argument
262 #define WPI_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->sc_mtx) argument
266 #define WPI_RXON_LOCK(_sc) mtx_lock(&(_sc)->rxon_mtx) argument
267 #define WPI_RXON_UNLOCK(_sc) mtx_unlock(&(_sc)->rxon_mtx) argument
273 #define WPI_TX_LOCK(_sc) mtx_lock(&(_sc)->tx_mtx) argument
274 #define WPI_TX_UNLOCK(_sc) mtx_unlock(&(_sc)->tx_mtx) argument
279 #define WPI_NT_LOCK(_sc) mtx_lock(&(_sc)->nt_mtx) argument
280 #define WPI_NT_UNLOCK(_sc) mtx_unlock(&(_sc)->nt_mtx) argument
285 #define WPI_TXQ_LOCK(_sc) mtx_lock(&(_sc)->txq_mtx) argument
[all …]
/freebsd-14.2/sys/dev/rtwn/rtl8812a/
H A Dr12a_var.h103 #define R12A_SOFTC(_sc) ((struct r12a_softc *)((_sc)->sc_priv)) argument
105 #define rtwn_r12a_fix_spur(_sc, _c) \ argument
106 ((R12A_SOFTC(_sc)->rs_fix_spur)((_sc), (_c)))
108 ((R12A_SOFTC(_sc)->rs_set_band_2ghz)((_sc), (_rates)))
110 ((R12A_SOFTC(_sc)->rs_set_band_5ghz)((_sc), (_rates)))
112 ((R12A_SOFTC(_sc)->rs_init_burstlen)((_sc)))
114 ((R12A_SOFTC(_sc)->rs_init_ampdu_fwhw)((_sc)))
116 ((R12A_SOFTC(_sc)->rs_crystalcap_write)((_sc)))
119 ((R12A_SOFTC(_sc)->rs_iq_calib_fw_supported)((_sc)))
121 #define rtwn_r12a_iq_calib_sw(_sc) \ argument
[all …]
/freebsd-14.2/sys/dev/bhnd/cores/pmu/
H A Dbhnd_pmu_private.h34 #define BHND_PMU_READ_4(_sc, _reg) (_sc)->io->rd4((_reg), (_sc)->io_ctx) argument
35 #define BHND_PMU_WRITE_4(_sc, _reg, _val) \ argument
36 (_sc)->io->wr4((_reg), (_val), (_sc)->io_ctx)
38 #define BHND_PMU_AND_4(_sc, _reg, _val) \ argument
39 BHND_PMU_WRITE_4((_sc), (_reg), \
41 #define BHND_PMU_OR_4(_sc, _reg, _val) \ argument
42 BHND_PMU_WRITE_4((_sc), (_reg), \
47 bhnd_pmu_ind_read((_sc)->io, (_sc)->io_ctx, \
50 bhnd_pmu_ind_write((_sc)->io, (_sc)->io_ctx, \
55 #define BHND_PMU_CCTRL_READ(_sc, _reg) \ argument
[all …]
/freebsd-14.2/sys/arm/freescale/vybrid/
H A Dvf_common.h29 #define READ4(_sc, _reg) \ argument
30 bus_space_read_4(_sc->bst, _sc->bsh, _reg)
31 #define WRITE4(_sc, _reg, _val) \ argument
32 bus_space_write_4(_sc->bst, _sc->bsh, _reg, _val)
33 #define READ2(_sc, _reg) \ argument
34 bus_space_read_2(_sc->bst, _sc->bsh, _reg)
35 #define WRITE2(_sc, _reg, _val) \ argument
36 bus_space_write_2(_sc->bst, _sc->bsh, _reg, _val)
37 #define READ1(_sc, _reg) \ argument
38 bus_space_read_1(_sc->bst, _sc->bsh, _reg)
[all …]
H A Dvf_edma.h111 #define TCD_READ4(_sc, _reg) \ argument
112 bus_space_read_4(_sc->bst_tcd, _sc->bsh_tcd, _reg)
113 #define TCD_WRITE4(_sc, _reg, _val) \ argument
114 bus_space_write_4(_sc->bst_tcd, _sc->bsh_tcd, _reg, _val)
115 #define TCD_READ2(_sc, _reg) \ argument
116 bus_space_read_2(_sc->bst_tcd, _sc->bsh_tcd, _reg)
117 #define TCD_WRITE2(_sc, _reg, _val) \ argument
118 bus_space_write_2(_sc->bst_tcd, _sc->bsh_tcd, _reg, _val)
119 #define TCD_READ1(_sc, _reg) \ argument
120 bus_space_read_1(_sc->bst_tcd, _sc->bsh_tcd, _reg)
[all …]
/freebsd-14.2/sys/dev/rtwn/rtl8192c/
H A Dr92c_var.h65 #define R92C_SOFTC(_sc) ((struct r92c_softc *)((_sc)->sc_priv)) argument
67 #define rtwn_r92c_set_bw20(_sc, _chan) \ argument
68 ((R92C_SOFTC(_sc)->rs_set_bw20)((_sc), (_chan)))
70 ((R92C_SOFTC(_sc)->rs_get_txpower)((_sc), (_chain), (_c), (_power)))
71 #define rtwn_r92c_set_gain(_sc, _gain) \ argument
72 ((R92C_SOFTC(_sc)->rs_set_gain)((_sc), (_gain)))
75 #define rtwn_r92c_tx_setup_hwseq(_sc, _buf) \ argument
76 ((R92C_SOFTC(_sc)->rs_tx_setup_hwseq)((_buf)))
77 #define rtwn_r92c_tx_setup_macid(_sc, _buf, _id) \ argument
79 #define rtwn_r92c_set_rom_opts(_sc, _buf) \ argument
[all …]
/freebsd-14.2/sys/dev/ath/
H A Dif_ath_rx.h40 (_sc)->sc_rx.recv_stop((_sc), (_dodelay))
41 #define ath_startrecv(_sc) \ argument
42 (_sc)->sc_rx.recv_start((_sc))
43 #define ath_rx_flush(_sc) \ argument
44 (_sc)->sc_rx.recv_flush((_sc))
45 #define ath_rxbuf_init(_sc, _bf) \ argument
46 (_sc)->sc_rx.recv_rxbuf_init((_sc), (_bf))
47 #define ath_rxdma_setup(_sc) \ argument
48 (_sc)->sc_rx.recv_setup(_sc)
49 #define ath_rxdma_teardown(_sc) \ argument
[all …]
H A Dif_athvar.h936 #define ATH_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->sc_mtx) argument
937 #define ATH_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx) argument
938 #define ATH_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx) argument
951 mtx_init(&(_sc)->sc_tx_mtx, (_sc)->sc_tx_mtx_name, \
955 #define ATH_TX_LOCK(_sc) mtx_lock(&(_sc)->sc_tx_mtx) argument
956 #define ATH_TX_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_tx_mtx) argument
986 mtx_init(&(_sc)->sc_pcu_mtx, (_sc)->sc_pcu_mtx_name, \
990 #define ATH_PCU_LOCK(_sc) mtx_lock(&(_sc)->sc_pcu_mtx) argument
1008 mtx_init(&(_sc)->sc_rx_mtx, (_sc)->sc_rx_mtx_name, \
1012 #define ATH_RX_LOCK(_sc) mtx_lock(&(_sc)->sc_rx_mtx) argument
[all …]
H A Dif_ath_tx.h154 #define ath_txdma_setup(_sc) \ argument
155 (_sc)->sc_tx.xmit_setup(_sc)
156 #define ath_txdma_teardown(_sc) \ argument
157 (_sc)->sc_tx.xmit_teardown(_sc)
158 #define ath_txq_restart_dma(_sc, _txq) \ argument
159 (_sc)->sc_tx.xmit_dma_restart((_sc), (_txq))
160 #define ath_tx_handoff(_sc, _txq, _bf) \ argument
161 (_sc)->sc_tx.xmit_handoff((_sc), (_txq), (_bf))
162 #define ath_draintxq(_sc, _rtype) \ argument
163 (_sc)->sc_tx.xmit_drain((_sc), (_rtype))
/freebsd-14.2/sys/arm/ti/
H A Dti_adcvar.h32 #define ADC_READ4(_sc, reg) bus_read_4((_sc)->sc_mem_res, reg) argument
33 #define ADC_WRITE4(_sc, reg, value) \ argument
73 #define TI_ADC_LOCK(_sc) \ argument
74 mtx_lock(&(_sc)->sc_mtx)
75 #define TI_ADC_UNLOCK(_sc) \ argument
76 mtx_unlock(&(_sc)->sc_mtx)
77 #define TI_ADC_LOCK_INIT(_sc) \ argument
78 mtx_init(&_sc->sc_mtx, device_get_nameunit(_sc->sc_dev), \
80 #define TI_ADC_LOCK_DESTROY(_sc) \ argument
81 mtx_destroy(&_sc->sc_mtx);
[all …]
H A Dti_spivar.h59 #define TI_SPI_WRITE(_sc, _off, _val) \ argument
60 bus_space_write_4((_sc)->sc_bst, (_sc)->sc_bsh, (_off), (_val))
61 #define TI_SPI_READ(_sc, _off) \ argument
62 bus_space_read_4((_sc)->sc_bst, (_sc)->sc_bsh, (_off))
64 #define TI_SPI_LOCK(_sc) \ argument
65 mtx_lock(&(_sc)->sc_mtx)
66 #define TI_SPI_UNLOCK(_sc) \ argument
67 mtx_unlock(&(_sc)->sc_mtx)
/freebsd-14.2/sys/arm/altera/socfpga/
H A Dsocfpga_common.h31 #define READ4(_sc, _reg) bus_read_4((_sc)->res[0], _reg) argument
32 #define READ2(_sc, _reg) bus_read_2((_sc)->res[0], _reg) argument
33 #define READ1(_sc, _reg) bus_read_1((_sc)->res[0], _reg) argument
34 #define WRITE4(_sc, _reg, _val) bus_write_4((_sc)->res[0], _reg, _val) argument
35 #define WRITE2(_sc, _reg, _val) bus_write_2((_sc)->res[0], _reg, _val) argument
36 #define WRITE1(_sc, _reg, _val) bus_write_1((_sc)->res[0], _reg, _val) argument
/freebsd-14.2/sys/dev/mwl/
H A Dif_mwlvar.h158 ((_sc)->sc_rxmem_paddr + MWL_JUMBO_OFFSET(_sc, _data))
342 mtx_init(&(_sc)->sc_mtx, device_get_nameunit((_sc)->sc_dev), \
344 #define MWL_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->sc_mtx) argument
345 #define MWL_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx) argument
346 #define MWL_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx) argument
347 #define MWL_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_mtx, MA_OWNED) argument
350 mtx_init(&(_sc)->sc_rxlock, device_get_nameunit((_sc)->sc_dev), \
352 #define MWL_RXFREE_DESTROY(_sc) mtx_destroy(&(_sc)->sc_rxlock) argument
353 #define MWL_RXFREE_LOCK(_sc) mtx_lock(&(_sc)->sc_rxlock) argument
354 #define MWL_RXFREE_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_rxlock) argument
[all …]
/freebsd-14.2/sys/dev/age/
H A Dif_agevar.h237 #define CSR_WRITE_4(_sc, reg, val) \ argument
239 #define CSR_WRITE_2(_sc, reg, val) \ argument
241 #define CSR_READ_2(_sc, reg) \ argument
242 bus_read_2((_sc)->age_res[0], (reg))
243 #define CSR_READ_4(_sc, reg) \ argument
244 bus_read_4((_sc)->age_res[0], (reg))
246 #define AGE_LOCK(_sc) mtx_lock(&(_sc)->age_mtx) argument
247 #define AGE_UNLOCK(_sc) mtx_unlock(&(_sc)->age_mtx) argument
248 #define AGE_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->age_mtx, MA_OWNED) argument
250 #define AGE_COMMIT_MBOX(_sc) \ argument
[all …]
/freebsd-14.2/sys/dev/etherswitch/mtkswitch/
H A Dmtkswitchvar.h40 #define MTK_IS_SWITCH(_sc, _type) \ argument
119 #define MTKSWITCH_LOCK(_sc) \ argument
120 mtx_lock(&(_sc)->sc_mtx)
121 #define MTKSWITCH_UNLOCK(_sc) \ argument
122 mtx_unlock(&(_sc)->sc_mtx)
124 mtx_assert(&(_sc)->sc_mtx, (_what))
125 #define MTKSWITCH_TRYLOCK(_sc) \ argument
126 mtx_trylock(&(_sc)->sc_mtx)
128 #define MTKSWITCH_READ(_sc, _reg) \ argument
129 bus_read_4((_sc)->sc_res, (_reg))
[all …]
/freebsd-14.2/sys/arm/ti/am335x/
H A Dam335x_ecap.c58 #define ECAP_READ2(_sc, reg) bus_read_2((_sc)->sc_mem_res, reg); argument
59 #define ECAP_WRITE2(_sc, reg, value) \ argument
60 bus_write_2((_sc)->sc_mem_res, reg, value);
61 #define ECAP_READ4(_sc, reg) bus_read_4((_sc)->sc_mem_res, reg); argument
62 #define ECAP_WRITE4(_sc, reg, value) \ argument
63 bus_write_4((_sc)->sc_mem_res, reg, value);
65 #define PWM_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx) argument
66 #define PWM_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx) argument
67 #define PWM_LOCK_INIT(_sc) mtx_init(&(_sc)->sc_mtx, \ argument
68 device_get_nameunit(_sc->sc_dev), "am335x_ecap softc", MTX_DEF)
[all …]
/freebsd-14.2/sys/dev/virtio/scsi/
H A Dvirtio_scsivar.h144 #define VTSCSI_MTX(_sc) &(_sc)->vtscsi_mtx argument
145 #define VTSCSI_LOCK_INIT(_sc, _name) mtx_init(VTSCSI_MTX(_sc), _name, \ argument
147 #define VTSCSI_LOCK(_sc) mtx_lock(VTSCSI_MTX(_sc)) argument
148 #define VTSCSI_UNLOCK(_sc) mtx_unlock(VTSCSI_MTX(_sc)) argument
149 #define VTSCSI_LOCK_OWNED(_sc) mtx_assert(VTSCSI_MTX(_sc), MA_OWNED) argument
150 #define VTSCSI_LOCK_NOTOWNED(_sc) mtx_assert(VTSCSI_MTX(_sc), MA_NOTOWNED) argument
151 #define VTSCSI_LOCK_DESTROY(_sc) mtx_destroy(VTSCSI_MTX(_sc)) argument
172 #define vtscsi_dprintf(_sc, _level, _msg, _args ...) do { \ argument
173 if ((_sc)->vtscsi_debug & (_level)) \
174 device_printf((_sc)->vtscsi_dev, "%s: "_msg, \
/freebsd-14.2/sys/arm/broadcom/bcm2835/
H A Dbcm2835_pwm.c76 bus_space_read_4(_sc->sc_m_bst, _sc->sc_m_bsh, _off)
80 bus_space_read_4(_sc->sc_c_bst, _sc->sc_c_bsh, _off)
82 #define W_CTL(_sc, _val) BCM_PWM_MEM_WRITE(_sc, 0x00, _val) argument
83 #define R_CTL(_sc) BCM_PWM_MEM_READ(_sc, 0x00) argument
84 #define W_STA(_sc, _val) BCM_PWM_MEM_WRITE(_sc, 0x04, _val) argument
85 #define R_STA(_sc) BCM_PWM_MEM_READ(_sc, 0x04) argument
86 #define W_RNG(_sc, _val) BCM_PWM_MEM_WRITE(_sc, 0x10, _val) argument
87 #define R_RNG(_sc) BCM_PWM_MEM_READ(_sc, 0x10) argument
89 #define R_DAT(_sc) BCM_PWM_MEM_READ(_sc, 0x14) argument
91 #define R_RNG2(_sc) BCM_PWM_MEM_READ(_sc, 0x20) argument
[all …]
H A Dbcm2835_spivar.h50 #define BCM_SPI_WRITE(_sc, _off, _val) \ argument
51 bus_space_write_4(_sc->sc_bst, _sc->sc_bsh, _off, _val)
52 #define BCM_SPI_READ(_sc, _off) \ argument
53 bus_space_read_4(_sc->sc_bst, _sc->sc_bsh, _off)
55 #define BCM_SPI_LOCK(_sc) \ argument
56 mtx_lock(&(_sc)->sc_mtx)
57 #define BCM_SPI_UNLOCK(_sc) \ argument
58 mtx_unlock(&(_sc)->sc_mtx)
H A Dbcm2835_bscvar.h59 #define BCM_BSC_WRITE(_sc, _off, _val) \ argument
60 bus_space_write_4((_sc)->sc_bst, (_sc)->sc_bsh, _off, _val)
61 #define BCM_BSC_READ(_sc, _off) \ argument
62 bus_space_read_4((_sc)->sc_bst, (_sc)->sc_bsh, _off)
64 #define BCM_BSC_LOCK(_sc) \ argument
65 mtx_lock(&(_sc)->sc_mtx)
66 #define BCM_BSC_UNLOCK(_sc) \ argument
67 mtx_unlock(&(_sc)->sc_mtx)
H A Dbcm2835_clkman.c66 #define BCM_CLKMAN_WRITE(_sc, _off, _val) \ argument
67 bus_space_write_4(_sc->sc_m_bst, _sc->sc_m_bsh, _off, _val)
68 #define BCM_CLKMAN_READ(_sc, _off) \ argument
69 bus_space_read_4(_sc->sc_m_bst, _sc->sc_m_bsh, _off)
71 #define W_CMCLK(_sc, unit, _val) BCM_CLKMAN_WRITE(_sc, unit, 0x5a000000 | (_val)) argument
72 #define R_CMCLK(_sc, unit) BCM_CLKMAN_READ(_sc, unit) argument
73 #define W_CMDIV(_sc, unit, _val) BCM_CLKMAN_WRITE(_sc, (unit) + 4, 0x5a000000 | (_val)) argument
74 #define R_CMDIV(_sc, unit) BCM_CLKMAN_READ(_sc, (unit) + 4) argument
/freebsd-14.2/sys/dev/alc/
H A Dif_alcvar.h260 #define CSR_WRITE_4(_sc, reg, val) \ argument
262 #define CSR_WRITE_2(_sc, reg, val) \ argument
264 #define CSR_WRITE_1(_sc, reg, val) \ argument
266 #define CSR_READ_2(_sc, reg) \ argument
267 bus_read_2((_sc)->alc_res[0], (reg))
268 #define CSR_READ_4(_sc, reg) \ argument
269 bus_read_4((_sc)->alc_res[0], (reg))
271 #define ALC_RXCHAIN_RESET(_sc) \ argument
279 #define ALC_LOCK(_sc) mtx_lock(&(_sc)->alc_mtx) argument
280 #define ALC_UNLOCK(_sc) mtx_unlock(&(_sc)->alc_mtx) argument
[all …]
/freebsd-14.2/sys/dev/stge/
H A Dif_stgereg.h89 #define CSR_WRITE_4(_sc, reg, val) \ argument
91 #define CSR_WRITE_2(_sc, reg, val) \ argument
93 #define CSR_WRITE_1(_sc, reg, val) \ argument
96 #define CSR_READ_4(_sc, reg) \ argument
98 #define CSR_READ_2(_sc, reg) \ argument
100 #define CSR_READ_1(_sc, reg) \ argument
667 #define STGE_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx) argument
668 #define STGE_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx) argument
669 #define STGE_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_mtx, MA_OWNED) argument
670 #define STGE_MII_LOCK(_sc) mtx_lock(&(_sc)->sc_mii_mtx) argument
[all …]
/freebsd-14.2/sys/dev/etherswitch/e6000sw/
H A De6000swreg.h51 #define MVSWITCH(_sc, id) ((_sc)->swid == (id)) argument
52 #define MVSWITCH_MULTICHIP(_sc) ((_sc)->sw_addr != 0) argument
59 #define REG_PORT(_sc, p) ((MVSWITCH((_sc), MV88E6190) ? 0 : 0x10) + (p)) argument
104 #define PORT_MASK(_sc) 0x7f argument
141 #define VTU_FID_MASK(_sc) (MVSWITCH((_sc), MV88E6190) ? 0xfff : 0xff) argument
147 #define VTU_PPREG(_sc) (MVSWITCH((_sc), MV88E6190) ? 8 : 4) argument
148 #define VTU_PORT(_sc, p) (((p) % VTU_PPREG(_sc)) * (16 / VTU_PPREG(_sc))) argument
177 #define ATU_PORT_MASK(_sc) (MVSWITCH((_sc), MV88E6190) ? 0xfff0 : 0xff0) argument

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