Searched refs:ZeroRHS (Results 1 – 2 of 2) sorted by relevance
| /freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | TargetLowering.cpp | 3374 APInt UndefRHS, ZeroRHS; in SimplifyDemandedVectorElts() local
3378 if (SimplifyDemandedVectorElts(RHS, DemandedRHS, UndefRHS, ZeroRHS, TLO, in SimplifyDemandedVectorElts()
3383 KnownZero = ZeroLHS & ZeroRHS; in SimplifyDemandedVectorElts()
3416 APInt UndefRHS, ZeroRHS; in SimplifyDemandedVectorElts() local
3420 if (SimplifyDemandedVectorElts(RHS, DemandedRHS, UndefRHS, ZeroRHS, TLO, in SimplifyDemandedVectorElts()
3463 if (ZeroRHS[M - NumElts]) in SimplifyDemandedVectorElts()
3541 APInt UndefRHS, ZeroRHS; in SimplifyDemandedVectorElts() local
3542 if (SimplifyDemandedVectorElts(Op1, DemandedElts, UndefRHS, ZeroRHS, TLO, in SimplifyDemandedVectorElts()
3550 KnownZero = ZeroLHS & ZeroRHS; in SimplifyDemandedVectorElts()
3568 APInt UndefRHS, ZeroRHS; in SimplifyDemandedVectorElts() local
[all …]
|
| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 45104 bool ZeroRHS = ISD::isBuildVectorAllZeros(RHS.getNode()); in combineSelect() local
45106 if ((SelectableLHS && ZeroRHS) || (SelectableRHS && ZeroLHS)) { in combineSelect()
|