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Searched refs:Zero64 (Results 1 – 6 of 6) sorted by relevance

/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPULegalizerInfo.cpp3789 Register Zero64; in buildMultiply() local
3797 if (!Zero64) in buildMultiply()
3798 Zero64 = B.buildConstant(S64, 0).getReg(0); in buildMultiply()
3799 return Zero64; in buildMultiply()
4454 auto Zero64 = B.buildConstant(S64, 0); in legalizeUnsignedDIV_REM64Impl() local
4455 auto NegDenom = B.buildSub(S64, Zero64, Denom); in legalizeUnsignedDIV_REM64Impl()
H A DAMDGPURegisterBankInfo.cpp2600 Register Zero64 = B.buildConstant(S64, 0).getReg(0); in applyMappingImpl() local
2601 MRI.setRegClass(Zero64, &AMDGPU::VReg_64RegClass); in applyMappingImpl()
2604 B.buildInstr(NewOpc, {DstReg, CarryOut}, {Op0L, Op1L, Zero64}); in applyMappingImpl()
H A DSIInstrInfo.cpp6402 Register Zero64 = MRI.createVirtualRegister(&AMDGPU::SReg_64RegClass); in extractRsrcPtr() local
6409 BuildMI(MBB, MI, MI.getDebugLoc(), TII.get(AMDGPU::S_MOV_B64), Zero64) in extractRsrcPtr()
6422 .addReg(Zero64) in extractRsrcPtr()
H A DAMDGPUISelLowering.cpp2048 SDValue Zero64 = DAG.getConstant(0, DL, VT); in LowerUDIVREM64() local
2054 SDValue Neg_RHS = DAG.getNode(ISD::SUB, DL, VT, Zero64, RHS); in LowerUDIVREM64()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZISelLowering.cpp8741 Register Zero64 = MRI.createVirtualRegister(&SystemZ::GR64BitRegClass); in emitExt128() local
8743 BuildMI(*MBB, MI, DL, TII->get(SystemZ::LLILL), Zero64) in emitExt128()
8746 .addReg(In128).addReg(Zero64).addImm(SystemZ::subreg_h64); in emitExt128()
/freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/
H A DLegalizerHelper.cpp6535 auto Zero64 = MIRBuilder.buildConstant(S64, 0); in lowerU64ToF32BitOps() local
6542 auto NotZero = MIRBuilder.buildICmp(CmpInst::ICMP_NE, S1, Src, Zero64); in lowerU64ToF32BitOps()