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Searched refs:ZR (Results 1 – 17 of 17) sorted by relevance

/freebsd-14.2/contrib/llvm-project/llvm/include/llvm/IR/
H A DInlineAsm.h268 ZR, enumerator
519 case ConstraintCode::ZR: in getMemConstraintName()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64SchedPredicates.td63 // Check for ZR in a register operand.
299 // ORR Rd, ZR, Rm, LSL #0
313 [// ORR Rd, ZR, #0
H A DAArch64SchedPredNeoverse.td50 def NeoverseMULIdiomPred : MCSchedPredicate< // <op> Rd, Rs, Rv, ZR
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMInstrThumb2.td5724 (Insn ZR, GPRwithZR:$fval, imm0_31:$imm)>;
5726 (Insn GPRwithZR:$tval, ZR, imm0_31:$imm)>;
5728 (Insn ZR, ZR, imm0_31:$imm)>;
5736 (t2CSINC ZR, ZR, imm0_31:$imm)>;
5738 (t2CSINV ZR, ZR, imm0_31:$imm)>;
5740 (t2CSINC ZR, ZR, (inv_cond_XFORM imm:$imm))>;
5742 (t2CSINV ZR, ZR, (inv_cond_XFORM imm:$imm))>;
5756 (t2CSINC $Rn, ZR, (inv_cond_XFORM imm:$imm))>;
5758 (t2CSEL ZR, $Rn, $imm)>;
5764 (t2CSINV rGPR:$Rd, ZR, ZR, pred_noal_inv:$fcond)>;
[all …]
H A DARMRegisterInfo.td212 def ZR : ARMReg<15, "zr">, DwarfRegNum<[15]>;
297 def GPRwithZR : RegisterClass<"ARM", [i32], 32, (add (sub GPR, PC), ZR)> {
H A DARMBaseRegisterInfo.cpp229 markSuperRegs(Reserved, ARM::ZR); in getReservedRegs()
H A DARMInstrMVE.td4337 (v16i1 (!cast<Instruction>("MVE_VCMP"#suffix#"8r") (v16i8 MQPR:$v1), ZR, fc))>;
4339 (v8i1 (!cast<Instruction>("MVE_VCMP"#suffix#"16r") (v8i16 MQPR:$v1), ZR, fc))>;
4341 (v4i1 (!cast<Instruction>("MVE_VCMP"#suffix#"32r") (v4i32 MQPR:$v1), ZR, fc))>;
4383 (v8i1 (MVE_VCMPf16r (v8f16 MQPR:$v1), ZR, fc))>;
4385 (v4i1 (MVE_VCMPf32r (v4f32 MQPR:$v1), ZR, fc))>;
4388 (v8i1 (MVE_VCMPf16r (v8f16 MQPR:$v1), ZR, fc, ARMVCCThen, VCCR:$p1, zero_reg))>;
4390 (v4i1 (MVE_VCMPf32r (v4f32 MQPR:$v1), ZR, fc, ARMVCCThen, VCCR:$p1, zero_reg))>;
6872 (v4i1 (MVE_VCMPf32r (v4f32 MQPR:$v1), ZR, ARMCCne))>;
6874 (v8i1 (MVE_VCMPf16r (v8f16 MQPR:$v1), ZR, ARMCCne))>;
6876 (v4i1 (MVE_VCMPf32r (v4f32 MQPR:$v1), ZR, ARMCCne))>;
[all …]
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZISelLowering.h542 return InlineAsm::ConstraintCode::ZR; in getInlineAsmMemConstraint()
H A DSystemZISelDAGToDAG.cpp1768 case InlineAsm::ConstraintCode::ZR: in SelectInlineAsmMemoryOperand()
/freebsd-14.2/contrib/sendmail/contrib/
H A Dmail.local.linux84 M49#ZR([4"!W=\08+28T/N1\7R8QT0`:`\H\&R8T!Z8U<4R0;^8F(Q59N@5J-
/freebsd-14.2/contrib/ncurses/include/
H A DCaps.hpux11721 exit_italics_mode ritm str ZR - - ----- End italic mode
H A DCaps.osf1r5651 exit_italics_mode ritm str ZR - - ----- End italic mode
H A DCaps713 exit_italics_mode ritm str ZR - - ----- End italic mode
H A DCaps.keys804 exit_italics_mode ritm str ZR - - ----- End italic mode
H A DCaps.aix4815 exit_italics_mode ritm str ZR - - ----- End italic mode
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/ARM/Disassembler/
H A DARMDisassembler.cpp1366 Inst.addOperand(MCOperand::createReg(ARM::ZR)); in DecodeGPRwithZRRegisterClass()
/freebsd-14.2/share/termcap/
H A Dtermcap2791 :ZH=\E[3m:ZR=\E[23m:
4698 :ZR=\E[23m:al=\E[L:bl=^G:bt=\E[Z:cb=\E[1K:cd=\E[J:ce=\E[K:\