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Searched refs:ZPR (Results 1 – 6 of 6) sorted by relevance

/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64SVEInstrInfo.td2661 def : Pat<(nxv2f16 (reinterpret_cast (nxv8f16 ZPR:$src))), (COPY_TO_REGCLASS ZPR:$src, ZPR)>;
2662 def : Pat<(nxv8f16 (reinterpret_cast (nxv2f16 ZPR:$src))), (COPY_TO_REGCLASS ZPR:$src, ZPR)>;
2663 def : Pat<(nxv4f16 (reinterpret_cast (nxv8f16 ZPR:$src))), (COPY_TO_REGCLASS ZPR:$src, ZPR)>;
2664 def : Pat<(nxv8f16 (reinterpret_cast (nxv4f16 ZPR:$src))), (COPY_TO_REGCLASS ZPR:$src, ZPR)>;
2665 def : Pat<(nxv2f32 (reinterpret_cast (nxv4f32 ZPR:$src))), (COPY_TO_REGCLASS ZPR:$src, ZPR)>;
2666 def : Pat<(nxv4f32 (reinterpret_cast (nxv2f32 ZPR:$src))), (COPY_TO_REGCLASS ZPR:$src, ZPR)>;
2667 def : Pat<(nxv2bf16 (reinterpret_cast (nxv8bf16 ZPR:$src))), (COPY_TO_REGCLASS ZPR:$src, ZPR)>;
2668 def : Pat<(nxv8bf16 (reinterpret_cast (nxv2bf16 ZPR:$src))), (COPY_TO_REGCLASS ZPR:$src, ZPR)>;
2669 def : Pat<(nxv4bf16 (reinterpret_cast (nxv8bf16 ZPR:$src))), (COPY_TO_REGCLASS ZPR:$src, ZPR)>;
3942 def : Pat<(Store (Ty ZPR:$vec0), (Ty ZPR:$vec1),
[all …]
H A DAArch64RegisterInfo.td1077 def ZPR : ZPRClass<31>;
1150 def ZSeqPairs : RegisterTuples<[zsub0, zsub1], [(rotl ZPR, 0), (rotl ZPR, 1)]>;
1151 def ZSeqTriples : RegisterTuples<[zsub0, zsub1, zsub2], [(rotl ZPR, 0), (rotl ZPR, 1), (rotl ZPR, 2…
1152 …RegisterTuples<[zsub0, zsub1, zsub2, zsub3], [(rotl ZPR, 0), (rotl ZPR, 1), (rotl ZPR, 2), (rotl Z…
1330 (trunc (rotl ZPR, 0), 8), (trunc (rotl ZPR, 8), 8)
1335 (trunc (rotl ZPR, 16), 8), (trunc (rotl ZPR, 24), 8)
1347 (trunc (rotl ZPR, 0), 4), (trunc (rotl ZPR, 4), 4),
1348 (trunc (rotl ZPR, 8), 4), (trunc (rotl ZPR, 12), 4)
1352 (trunc (rotl ZPR, 16), 4), (trunc (rotl ZPR, 20), 4),
1353 (trunc (rotl ZPR, 24), 4), (trunc (rotl ZPR, 28), 4)
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H A DSVEInstrFormats.td1728 def : Pat<(nxv16i8 (op (nxv16i8 ZPR:$Zn), (i32 (vector_extract (nxv16i8 ZPR:$Vm), 0)))),
1730 def : Pat<(nxv8i16 (op (nxv8i16 ZPR:$Zn), (i32 (vector_extract (nxv8i16 ZPR:$Vm), 0)))),
1732 def : Pat<(nxv4i32 (op (nxv4i32 ZPR:$Zn), (i32 (vector_extract (nxv4i32 ZPR:$Vm), 0)))),
1734 def : Pat<(nxv2i64 (op (nxv2i64 ZPR:$Zn), (i64 (vector_extract (nxv2i64 ZPR:$Vm), 0)))),
5052 ZPR:$Zd),
6524 (!cast<Instruction>(NAME # _UXTW) ZPR:$data, PPR:$gp, GPR64sp:$base, ZPR:$offsets)>;
6595 (!cast<Instruction>(NAME) ZPR:$data, PPR:$gp, GPR64sp:$base, ZPR:$offsets)>;
6635 def : Pat<(op (nxv4i32 ZPR:$data), (nxv4i1 PPR:$gp), (nxv4i32 ZPR:$ptrs), imm_ty:$index, vt),
6636 (!cast<Instruction>(NAME # _IMM) ZPR:$data, PPR:$gp, ZPR:$ptrs, imm_ty:$index)>;
6652 def : Pat<(op (nxv2i64 ZPR:$data), (nxv2i1 PPR:$gp), (nxv2i64 ZPR:$ptrs), imm_ty:$index, vt),
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H A DAArch64FrameLowering.cpp2757 enum RegType { GPR, FPR64, FPR128, PPR, ZPR } Type; enumerator
2770 case ZPR: in getScale()
2777 bool isScalable() const { return Type == PPR || Type == ZPR; } in isScalable()
2831 RPI.Type = RegPairInfo::ZPR; in computeCalleeSaveRegisterPairs()
2860 case RegPairInfo::ZPR: in computeCalleeSaveRegisterPairs()
3038 case RegPairInfo::ZPR: in spillCalleeSavedRegisters()
3090 if (RPI.Type == RegPairInfo::ZPR || RPI.Type == RegPairInfo::PPR) in spillCalleeSavedRegisters()
3142 case RegPairInfo::ZPR: in restoreCalleeSavedRegisters()
/freebsd-14.2/sys/contrib/device-tree/Bindings/mmc/
H A Dmarvell,xenon-sdhci.txt66 Set PHY ZPR value.
69 ZPR is set as 0xF by default if this property is not provided.
H A Dmarvell,xenon-sdhci.yaml102 Set PHY ZPR value.