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Searched refs:ZIP1 (Results 1 – 7 of 7) sorted by relevance

/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64SchedKryoDetails.td2329 (instregex "((TRN1|TRN2|ZIP1|UZP1|UZP2)v2i64|ZIP2(v2i64|v4i32|v8i16|v16i8))")>;
2365 (instregex "(UZP1|UZP2|ZIP1|ZIP2)(v2i32|v4i16|v8i8)")>;
2377 (instregex "ZIP1(v4i32|v8i16|v16i8)")>;
H A DAArch64ISelLowering.h198 ZIP1, enumerator
H A DAArch64SchedFalkorDetails.td920 def : InstRW<[FalkorWr_1VXVY_1cyc], (instregex "^(TRN1|TRN2|ZIP1|UZP1|UZP2|ZIP2|XTN)(v2i32|v2i64|…
H A DAArch64ISelLowering.cpp2444 MAKE_CASE(AArch64ISD::ZIP1) in getTargetNodeName()
5221 return DAG.getNode(AArch64ISD::ZIP1, dl, Op.getValueType(), in LowerINTRINSIC_WO_CHAIN()
11884 return DAG.getNode(AArch64ISD::ZIP1, dl, VT, OpLHS, OpRHS); in GeneratePerfectShuffle()
12282 unsigned Opc = (WhichResult == 0) ? AArch64ISD::ZIP1 : AArch64ISD::ZIP2; in LowerVECTOR_SHUFFLE()
12295 unsigned Opc = (WhichResult == 0) ? AArch64ISD::ZIP1 : AArch64ISD::ZIP2; in LowerVECTOR_SHUFFLE()
18320 if (N->getNumOperands() == 2 && N0Opc == AArch64ISD::ZIP1 && in performConcatVectorsCombine()
18327 return DAG.getNode(AArch64ISD::ZIP1, dl, VT, E0, E1); in performConcatVectorsCombine()
21423 SDValue Zipped = DAG.getNode(AArch64ISD::ZIP1, DL, VecVT, in vectorToScalarBitmask()
26497 SDValue Lo = DAG.getNode(AArch64ISD::ZIP1, DL, OpVT, Op.getOperand(0), in LowerVECTOR_INTERLEAVE()
26701 DAG, VT, DAG.getNode(AArch64ISD::ZIP1, DL, ContainerVT, Op1, Op2)); in LowerFixedLengthVECTOR_SHUFFLEToSVE()
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H A DAArch64SchedThunderX3T110.td1643 (instregex "^UZP1", "^UZP2", "^ZIP1", "^ZIP2")>;
H A DAArch64SchedA64FX.td1695 (instregex "^UZP1", "^UZP2", "^ZIP1", "^ZIP2")>;
H A DAArch64InstrInfo.td702 def AArch64zip1 : SDNode<"AArch64ISD::ZIP1", SDT_AArch64Zip>;
6049 defm ZIP1 : SIMDZipVector<0b011, "zip1", AArch64zip1>;