| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.h | 866 bool shouldTransformSignedTruncationCheck(EVT XVT, in shouldTransformSignedTruncationCheck() argument
869 if (XVT.isVector()) in shouldTransformSignedTruncationCheck()
880 return VTIsOk(XVT) && VTIsOk(KeptBitsVT); in shouldTransformSignedTruncationCheck()
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| H A D | AArch64ISelLowering.cpp | 6070 EVT XVT, ExpVT; in LowerFLDEXP() local
6078 XVT = MVT::nxv4f32; in LowerFLDEXP()
6082 XVT = MVT::nxv2f64; in LowerFLDEXP()
6090 DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, XVT, DAG.getUNDEF(XVT), X, Zero); in LowerFLDEXP()
6093 SDValue VPg = getPTrue(DAG, DL, XVT.changeVectorElementType(MVT::i1), in LowerFLDEXP()
6096 DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, XVT, in LowerFLDEXP()
19394 EVT XVT = Op0.getOperand(0).getValueType(); in areLoadedOffsetButOtherwiseSame() local
19395 if (XVT.getScalarSizeInBits() != 8 && XVT.getScalarSizeInBits() != 16 && in areLoadedOffsetButOtherwiseSame()
19396 XVT.getScalarSizeInBits() != 32) in areLoadedOffsetButOtherwiseSame()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.h | 1154 shouldTransformSignedTruncationCheck(EVT XVT, in shouldTransformSignedTruncationCheck() argument
1157 if (XVT.isVector()) in shouldTransformSignedTruncationCheck()
1168 return VTIsOk(XVT) && VTIsOk(KeptBitsVT); in shouldTransformSignedTruncationCheck()
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| H A D | X86ISelDAGToDAG.cpp | 2001 MVT XVT = X.getSimpleValueType(); in foldMaskAndShiftToExtract() local
2005 SDValue NewMask = DAG.getConstant(0xff, DL, XVT); in foldMaskAndShiftToExtract()
2006 SDValue Srl = DAG.getNode(ISD::SRL, DL, XVT, X, Eight); in foldMaskAndShiftToExtract()
2007 SDValue And = DAG.getNode(ISD::AND, DL, XVT, Srl, NewMask); in foldMaskAndShiftToExtract()
2189 MVT XVT = X.getSimpleValueType(); in foldMaskAndShiftToScale() local
2192 SDValue NewSRL = DAG.getNode(ISD::SRL, DL, XVT, X, NewSRLAmt); in foldMaskAndShiftToScale()
2248 MVT XVT = X.getSimpleValueType(); in foldMaskedShiftToBEXTR() local
2252 SDValue NewSRL = DAG.getNode(ISD::SRL, DL, XVT, X, NewSRLAmt); in foldMaskedShiftToBEXTR()
3972 MVT XVT = X.getSimpleValueType(); in matchBitExtract() local
4008 if (XVT != MVT::i32) { in matchBitExtract()
[all …]
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.h | 638 bool shouldTransformSignedTruncationCheck(EVT XVT,
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| H A D | RISCVISelLowering.cpp | 16096 EVT XVT, unsigned KeptBits) const { in shouldTransformSignedTruncationCheck() argument
16098 if (XVT.isVector()) in shouldTransformSignedTruncationCheck()
16101 if (XVT != MVT::i32 && XVT != MVT::i64) in shouldTransformSignedTruncationCheck()
16110 ((KeptBits == 8 && XVT == MVT::i64 && !Subtarget.is64Bit()) || in shouldTransformSignedTruncationCheck()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | TargetLowering.cpp | 4033 EVT XVT = X.getValueType(); in optimizeSetCCOfSignedTruncationCheck() local
4068 assert(XVT.isInteger()); in optimizeSetCCOfSignedTruncationCheck()
4069 NewCond = getSetCCInverse(NewCond, XVT); in optimizeSetCCOfSignedTruncationCheck()
4082 assert(KeptBits > 0 && KeptBits < XVT.getSizeInBits() && "unreachable"); in optimizeSetCCOfSignedTruncationCheck()
4087 XVT, KeptBits)) in optimizeSetCCOfSignedTruncationCheck()
4090 const unsigned MaskedBits = XVT.getSizeInBits() - KeptBits; in optimizeSetCCOfSignedTruncationCheck()
4091 assert(MaskedBits > 0 && MaskedBits < XVT.getSizeInBits() && "unreachable"); in optimizeSetCCOfSignedTruncationCheck()
4095 SDValue ShiftAmt = DAG.getConstant(MaskedBits, DL, XVT); in optimizeSetCCOfSignedTruncationCheck()
4096 SDValue T0 = DAG.getNode(ISD::SHL, DL, XVT, X, ShiftAmt); in optimizeSetCCOfSignedTruncationCheck()
4097 SDValue T1 = DAG.getNode(ISD::SRA, DL, XVT, T0, ShiftAmt); in optimizeSetCCOfSignedTruncationCheck()
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| H A D | DAGCombiner.cpp | 5774 EVT XVT = X.getValueType(); in hoistLogicOpWithSameOpcodeHands() local
5784 if (XVT != Y.getValueType()) in hoistLogicOpWithSameOpcodeHands()
5789 !TLI.isOperationLegalOrCustom(LogicOpcode, XVT)) in hoistLogicOpWithSameOpcodeHands()
5798 SDValue Logic = DAG.getNode(LogicOpcode, DL, XVT, X, Y); in hoistLogicOpWithSameOpcodeHands()
5811 if (XVT != Y.getValueType()) in hoistLogicOpWithSameOpcodeHands()
5818 if (TLI.isZExtFree(VT, XVT) && TLI.isTruncateFree(XVT, VT)) in hoistLogicOpWithSameOpcodeHands()
5820 if (!TLI.isTypeLegal(XVT)) in hoistLogicOpWithSameOpcodeHands()
5822 SDValue Logic = DAG.getNode(LogicOpcode, DL, XVT, X, Y); in hoistLogicOpWithSameOpcodeHands()
5872 if (XVT.isInteger() && XVT == Y.getValueType() && in hoistLogicOpWithSameOpcodeHands()
5874 !XVT.isVector() && !TLI.isTypeLegal(XVT))) { in hoistLogicOpWithSameOpcodeHands()
[all …]
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| /freebsd-14.2/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | TargetLowering.h | 780 virtual bool shouldTransformSignedTruncationCheck(EVT XVT, in shouldTransformSignedTruncationCheck() argument
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUISelLowering.cpp | 3978 EVT XVT = X.getValueType(); in performShlCombine() local
3979 SDValue Shl = DAG.getNode(ISD::SHL, SL, XVT, X, SDValue(RHS, 0)); in performShlCombine()
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