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Searched refs:XMM (Results 1 – 21 of 21) sorted by relevance

/freebsd-14.2/crypto/openssl/crypto/aes/asm/
H A Dbsaes-armv7.pl808 veor @XMM[6], @XMM[6], @XMM[8]
809 veor @XMM[4], @XMM[4], @XMM[8]
810 veor @XMM[2], @XMM[2], @XMM[8]
811 veor @XMM[7], @XMM[7], @XMM[8]
812 veor @XMM[3], @XMM[3], @XMM[8]
813 veor @XMM[5], @XMM[5], @XMM[8]
814 veor @XMM[0], @XMM[0], @XMM[8]
815 veor @XMM[1], @XMM[1], @XMM[8]
910 veor @XMM[4], @XMM[4], @XMM[8]
911 veor @XMM[6], @XMM[6], @XMM[8]
[all …]
H A Dbsaes-x86_64.pl828 pxor @XMM[9], @XMM[1]
829 pxor @XMM[9], @XMM[2]
830 pxor @XMM[9], @XMM[3]
833 pxor @XMM[9], @XMM[4]
834 pxor @XMM[9], @XMM[5]
837 pxor @XMM[9], @XMM[6]
838 pxor @XMM[9], @XMM[7]
872 pxor @XMM[8], @XMM[4]
873 pxor @XMM[8], @XMM[6]
874 pxor @XMM[8], @XMM[3]
[all …]
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86InstrXOP.td20 Sched<[SchedWriteVecALU.XMM.Folded, SchedWriteVecALU.XMM.ReadAfterFold]>;
80 SchedWriteFRnd.XMM>;
89 SchedWriteFRnd.XMM>;
158 SchedWriteVecShiftImm.XMM>;
160 SchedWriteVecShiftImm.XMM>;
162 SchedWriteVecShiftImm.XMM>;
164 SchedWriteVecShiftImm.XMM>;
324 SchedWriteVarShuffle.XMM>;
369 SchedWriteShuffle.XMM>;
459 SchedWriteFVarShuffle.XMM>;
[all …]
H A DX86Schedule.td84 X86FoldableSchedWrite XMM = s128; // XMM operations.
120 X86SchedWriteMoveLS XMM = s128; // XMM operations.
245 defm WriteFAddX : X86SchedWritePair<ReadAfterVecXLd>; // Floating point add/sub (XMM).
253 defm WriteFCmpX : X86SchedWritePair<ReadAfterVecXLd>; // Floating point compare (XMM).
296 defm WriteFMAX : X86SchedWritePair<ReadAfterVecXLd>; // Fused Multiply Add (XMM).
388 defm WriteShuffleX : X86SchedWritePair<ReadAfterVecXLd>; // Vector shuffles (XMM).
402 defm WritePSADBWX : X86SchedWritePair<ReadAfterVecXLd>; // Vector PSADBW (XMM).
423 defm WriteCvtPD2I : X86SchedWritePair<ReadAfterVecXLd>; // Double -> Integer (XMM).
428 defm WriteCvtPS2I : X86SchedWritePair<ReadAfterVecXLd>; // Float -> Integer (XMM).
433 defm WriteCvtI2PD : X86SchedWritePair<ReadAfterVecXLd>; // Integer -> Double (XMM).
[all …]
H A DX86InstrSSE.td670 Sched<[SchedWriteFShuffle.XMM.Folded, SchedWriteFShuffle.XMM.ReadAfterFold]>;
678 Sched<[SchedWriteFShuffle.XMM.Folded, SchedWriteFShuffle.XMM.ReadAfterFold]>;
1035 // and/or XMM operand(s).
1569 // XMM only
1648 // XMM only
1789 // XMM only
3606 OpNode, OpNode2, VR128, sched.XMM, schedImm.XMM,
3615 VR128, sched.XMM, schedImm.XMM, DstVT128, SrcVT,
4365 // Moving from XMM to XMM and clear upper 64 bits. Note, there is a bug in
5456 Sched<[SchedWriteFShuffle.XMM.Folded, SchedWriteFShuffle.XMM.ReadAfterFold]>;
[all …]
H A DX86CallingConv.td46 list<Register> XMM = [];
138 // float, double, float128 --> XMM
141 CCIfSubtarget<"hasSSE1()", CCAssignToReg<RC.XMM>>>,
146 // __m128, __m128i, __m128d --> XMM
149 CCIfSubtarget<"hasSSE1()", CCAssignToReg<RC.XMM>>>,
220 // float, double, float128 --> XMM
222 CCIfSubtarget<"hasSSE1()", CCAssignToReg<RC.XMM>>>,
224 // __m128, __m128i, __m128d --> XMM
795 // SSE vector arguments are passed in XMM registers.
815 // SSE vector arguments are passed in XMM registers.
[all …]
H A DX86ScheduleZnver3.td890 defm : Zn3WriteResXMMPair<WriteFAddX, [Zn3FPFAdd01], 3, [1], 1>; // Floating point add/sub (XMM).
941 defm : Zn3WriteResXMMPair<WriteFMAX, [Zn3FPFMul01], 4, [1], 1>; // Fused Multiply Add (XMM).
1119 defm : Zn3WriteResXMMPair<WriteShuffleX, [Zn3FPVShuf01], 1, [1], 1>; // Vector shuffles (XMM).
1133 defm : Zn3WriteResXMMPair<WritePSADBWX, [Zn3FPVAdd0123], 3, [2], 1>; // Vector PSADBW (XMM).
1154 defm : Zn3WriteResXMMPair<WriteCvtPD2I, [Zn3FPFCvt01], 3, [1], 1>; // Double -> Integer (XMM).
1167 defm : Zn3WriteResXMMPair<WriteCvtPS2I, [Zn3FPFCvt01], 3, [1], 1>; // Float -> Integer (XMM).
1172 defm : Zn3WriteResXMMPair<WriteCvtI2PD, [Zn3FPFCvt01], 3, [1], 1>; // Integer -> Double (XMM).
1184 defm : Zn3WriteResXMMPair<WriteCvtI2PS, [Zn3FPFCvt01], 3, [1], 1>; // Integer -> Float (XMM).
1554 // SSE XMM Zero-idioms.
1569 // AVX XMM Zero-idioms.
[all …]
H A DX86ScheduleZnver4.td904 defm : Zn4WriteResXMMPair<WriteFAddX, [Zn4FPFAdd01], 3, [1], 1>; // Floating point add/sub (XMM).
955 defm : Zn4WriteResXMMPair<WriteFMAX, [Zn4FPFMul01], 4, [1], 1>; // Fused Multiply Add (XMM).
1165 defm : Zn4WriteResXMMPair<WriteShuffleX, [Zn4FPVShuf01], 1, [1], 1>; // Vector shuffles (XMM).
1179 defm : Zn4WriteResXMMPair<WritePSADBWX, [Zn4FPVAdd0123], 3, [2], 1>; // Vector PSADBW (XMM).
1200 defm : Zn4WriteResXMMPair<WriteCvtPD2I, [Zn4FPFCvt01], 3, [2], 1>; // Double -> Integer (XMM).
1211 defm : Zn4WriteResXMMPair<WriteCvtPS2I, [Zn4FPFCvt01], 3, [1], 1>; // Float -> Integer (XMM).
1216 defm : Zn4WriteResXMMPair<WriteCvtI2PD, [Zn4FPFCvt01], 3, [1], 1>; // Integer -> Double (XMM).
1227 defm : Zn4WriteResXMMPair<WriteCvtI2PS, [Zn4FPFCvt01], 3, [1], 1>; // Integer -> Float (XMM).
1887 // SSE XMM Zero-idioms.
1902 // AVX XMM Zero-idioms.
[all …]
H A DX86InstrFMA.td106 VR128, OpTy128, f128mem, MemFrag128, Op, sched.XMM>;
108 VR128, OpTy128, f128mem, MemFrag128, Op, sched.XMM>;
110 VR128, OpTy128, f128mem, MemFrag128, Op, sched.XMM>;
477 REX_W, Sched<[sched.XMM]>;
484 Sched<[sched.XMM.Folded, sched.XMM.ReadAfterFold, sched.XMM.ReadAfterFold]>;
491 Sched<[sched.XMM.Folded, sched.XMM.ReadAfterFold,
496 sched.XMM.ReadAfterFold]>;
530 Sched<[sched.XMM]>;
H A DX86SchedBroadwell.td262 defm : BWWriteResPair<WriteFAddX, [BWPort1], 3, [1], 1, 5>; // Floating point add/sub (XMM).
266 …m : BWWriteResPair<WriteFAdd64X, [BWPort1], 3, [1], 1, 5>; // Floating point double add/sub (XMM).
271 defm : BWWriteResPair<WriteFCmpX, [BWPort1], 3, [1], 1, 5>; // Floating point compare (XMM).
275 …m : BWWriteResPair<WriteFCmp64X, [BWPort1], 3, [1], 1, 5>; // Floating point double compare (XMM).
283 …m : BWWriteResPair<WriteFMulX, [BWPort01], 3, [1], 1, 5>; // Floating point multiplication (XMM).
287 …riteResPair<WriteFMul64X, [BWPort01], 3, [1], 1, 5>; // Floating point double multiplication (XMM).
292 …teResPair<WriteFDivX, [BWPort0,BWFPDivider], 11, [1,5], 1, 5>; // Floating point division (XMM).
296 …teResPair<WriteFDiv64X, [BWPort0,BWFPDivider], 14, [1,8], 1, 5>; // Floating point division (XMM).
301 …BWWriteResPair<WriteFRcpX, [BWPort0], 5, [1], 1, 5>; // Floating point reciprocal estimate (XMM).
323 defm : BWWriteResPair<WriteFMAX, [BWPort01], 5, [1], 1, 5>; // Fused Multiply Add (XMM).
[all …]
H A DX86InstrAVX512.td649 // vinsertps - insert f32 to XMM
656 EVEX, VVVV, Sched<[SchedWriteFShuffle.XMM]>;
664 Sched<[SchedWriteFShuffle.XMM.Folded, SchedWriteFShuffle.XMM.ReadAfterFold]>;
1000 // vextractps - extract 32 bits from XMM
4294 Sched<[SchedWriteFShuffle.XMM]>;
4303 Sched<[SchedWriteFShuffle.XMM]>;
4310 Sched<[SchedWriteFShuffle.XMM]>;
6456 Sched<[SchedWriteFShuffle.XMM]>, EVEX, VVVV;
6481 … Sched<[SchedWriteFShuffle.XMM.Folded, SchedWriteFShuffle.XMM.ReadAfterFold]>, EVEX, VVVV;
9308 sched.XMM>,
[all …]
H A DX86RegisterInfo.td341 // XMM Registers, used by the various SSE instruction set extensions.
385 def YMM#Index : X86Reg<"ymm"#Index, Index, [!cast<X86Reg>("XMM"#Index)]>,
386 DwarfRegAlias<!cast<X86Reg>("XMM"#Index)>;
391 def YMM#Index : X86Reg<"ymm"#Index, Index, [!cast<X86Reg>("XMM"#Index)]>,
392 DwarfRegAlias<!cast<X86Reg>("XMM"#Index)>;
401 DwarfRegAlias<!cast<X86Reg>("XMM"#Index)>;
735 def FR32 : RegisterClass<"X86", [f32], 32, (sequence "XMM%u", 0, 15)>;
799 def FR32X : RegisterClass<"X86", [f32], 32, (sequence "XMM%u", 0, 31)>;
H A DX86ScheduleZnver1.td890 //=== Integer MMX and XMM Instructions ===//
985 //=== Floating Point XMM and YMM Instructions ===//
1348 // AVX XMM Zero-idioms.
1386 // AVX XMM
H A DX86ScheduleZnver2.td900 //=== Integer MMX and XMM Instructions ===//
993 //=== Floating Point XMM and YMM Instructions ===//
1354 // AVX XMM Zero-idioms.
1392 // AVX XMM
H A DX86InstrMMX.td232 let SchedRW = [SchedWriteVecMoveLS.XMM.RR] in {
H A DX86SchedHaswell.td859 //=== Floating Point XMM and YMM Instructions ===//
/freebsd-14.2/sys/cddl/dev/dtrace/x86/
H A Ddis_tables.c750 /* [54] */ TNSZ("andpd",XMM,16), TNSZ("andnpd",XMM,16), TNSZ("orpd",XMM,16), TNSZ("xorpd",XMM,16),
751 /* [58] */ TNSZ("addpd",XMM,16), TNSZ("mulpd",XMM,16), TNSZ("cvtpd2ps",XMM,16),TNSZ("cvtps2dq",XM…
752 /* [5C] */ TNSZ("subpd",XMM,16), TNSZ("minpd",XMM,16), TNSZ("divpd",XMM,16), TNSZ("maxpd",XMM,16),
789 /* [D0] */ TNSZ("addsubpd",XMM,16),TNSZ("psrlw",XMM,16), TNSZ("psrld",XMM,16), TNSZ("psrlq",XMM,1…
791 /* [D8] */ TNSZ("psubusb",XMM,16), TNSZ("psubusw",XMM,16), TNSZ("pminub",XMM,16), TNSZ("pand",XMM…
794 /* [E0] */ TNSZ("pavgb",XMM,16), TNSZ("psraw",XMM,16), TNSZ("psrad",XMM,16), TNSZ("pavgw",XMM,16),
796 /* [E8] */ TNSZ("psubsb",XMM,16), TNSZ("psubsw",XMM,16), TNSZ("pminsw",XMM,16), TNSZ("por",XMM,16…
797 /* [EC] */ TNSZ("paddsb",XMM,16), TNSZ("paddsw",XMM,16), TNSZ("pmaxsw",XMM,16), TNSZ("pxor",XMM,1…
801 /* [F8] */ TNSZ("psubb",XMM,16), TNSZ("psubw",XMM,16), TNSZ("psubd",XMM,16), TNSZ("psubq",XMM,16),
919 /* [5C] */ TNSZ("subsd",XMM,8), TNSZ("minsd",XMM,8), TNSZ("divsd",XMM,8), TNSZ("maxsd",XMM,8),
[all …]
/freebsd-14.2/crypto/openssl/doc/man3/
H A DOPENSSL_ia32cap.pod32 =item bit #24, FXSR bit, denoting availability of XMM registers;
66 clearing bit #24 disables SSE2 code operating on 128-bit XMM register
69 enable XMM registers. Historically address of the capability vector copy
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64CallingConvention.td257 // The first 4 FP/Vector arguments are passed in XMM registers.
321 // can only be used by ABI non-compliant code. If the target doesn't have XMM
/freebsd-14.2/crypto/openssl/
H A DNEWS.md79 * Fix POLY1305 MAC implementation corrupting XMM registers on Windows
H A DCHANGES.md219 depend on the contents of non-volatile XMM registers at all, to the worst
254 * Fix POLY1305 MAC implementation corrupting XMM registers on Windows.
257 does not save the contents of non-volatile XMM registers on Windows 64
259 returning to the caller all the XMM registers are set to zero rather than
265 depend on the contents of non-volatile XMM registers at all, to the worst