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Searched refs:XLenVT (Results 1 – 25 of 27) sorted by relevance

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/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVGISel.td19 def simm12Plus1 : ImmLeaf<XLenVT, [{
26 def simm12Minus1Nonzero : ImmLeaf<XLenVT, [{
29 def simm12Minus1NonzeroNonNeg1 : ImmLeaf<XLenVT, [{
86 def : Pat<(XLenVT (sub GPR:$rs1, simm12Plus1:$imm)),
99 def PtrVT : PtrValueTypeByHwMode<XLenVT, 0>;
113 foreach Ty = [PtrVT, XLenVT] in {
117 def : Pat<(XLenVT (seteq (Ty GPR:$rs1), (Ty GPR:$rs2))),
119 def : Pat<(XLenVT (setne (Ty GPR:$rs1), (Ty 0))), (SLTU (XLenVT X0), GPR:$rs1)>;
122 def : Pat<(XLenVT (setne (Ty GPR:$rs1), (Ty GPR:$rs2))),
123 (SLTU (XLenVT X0), (XOR GPR:$rs1, GPR:$rs2))>;
[all …]
H A DRISCVInstrInfoZb.td544 def : Pat<(XLenVT (and (not (shiftop<shl> 1, (XLenVT GPR:$rs2))), GPR:$rs1)),
546 def : Pat<(XLenVT (and (rotl -2, (XLenVT GPR:$rs2)), GPR:$rs1)),
548 def : Pat<(XLenVT (or (shiftop<shl> 1, (XLenVT GPR:$rs2)), GPR:$rs1)),
550 def : Pat<(XLenVT (xor (shiftop<shl> 1, (XLenVT GPR:$rs2)), GPR:$rs1)),
552 def : Pat<(XLenVT (and (shiftop<srl> GPR:$rs1, (XLenVT GPR:$rs2)), 1)),
555 def : Pat<(XLenVT (shiftop<shl> 1, (XLenVT GPR:$rs2))),
557 def : Pat<(XLenVT (not (shiftop<shl> -1, (XLenVT GPR:$rs2)))),
567 def : Pat<(XLenVT (and (srl GPR:$rs1, uimmlog2xlen:$shamt), (XLenVT 1))),
570 def : Pat<(XLenVT (seteq (XLenVT (and GPR:$rs1, SingleBitSetMask:$mask)), 0)),
642 def : Pat<(or (shl (zexti8 (XLenVT GPR:$rs2)), (XLenVT 8)),
[all …]
H A DRISCVInstrInfoZicond.td37 def : Pat<(XLenVT (riscv_czero_eqz GPR:$rs1, GPR:$rc)),
39 def : Pat<(XLenVT (riscv_czero_nez GPR:$rs1, GPR:$rc)),
42 def : Pat<(XLenVT (riscv_czero_eqz GPR:$rs1, (riscv_setne (XLenVT GPR:$rc)))),
44 def : Pat<(XLenVT (riscv_czero_eqz GPR:$rs1, (riscv_seteq (XLenVT GPR:$rc)))),
46 def : Pat<(XLenVT (riscv_czero_nez GPR:$rs1, (riscv_setne (XLenVT GPR:$rc)))),
48 def : Pat<(XLenVT (riscv_czero_nez GPR:$rs1, (riscv_seteq (XLenVT GPR:$rc)))),
H A DRISCVInstrInfoXTHead.td647 def : Pat<(select (XLenVT GPR:$cond), (XLenVT GPR:$a), (XLenVT GPR:$b)),
649 def : Pat<(select (XLenVT GPR:$cond), (XLenVT GPR:$a), (XLenVT 0)),
651 def : Pat<(select (XLenVT GPR:$cond), (XLenVT 0), (XLenVT GPR:$b)),
654 def : Pat<(select (riscv_seteq (XLenVT GPR:$cond)), (XLenVT GPR:$a), (XLenVT GPR:$b)),
656 def : Pat<(select (riscv_setne (XLenVT GPR:$cond)), (XLenVT GPR:$a), (XLenVT GPR:$b)),
658 def : Pat<(select (riscv_seteq (XLenVT GPR:$cond)), (XLenVT GPR:$a), (XLenVT 0)),
660 def : Pat<(select (riscv_setne (XLenVT GPR:$cond)), (XLenVT GPR:$a), (XLenVT 0)),
662 def : Pat<(select (riscv_seteq (XLenVT GPR:$cond)), (XLenVT 0), (XLenVT GPR:$b)),
664 def : Pat<(select (riscv_setne (XLenVT GPR:$cond)), (XLenVT 0), (XLenVT GPR:$b)),
722 def uimm2_3 : Operand<XLenVT>, ImmLeaf<XLenVT, [{
[all …]
H A DRISCVInstrInfo.td374 def ixlenimm : Operand<XLenVT>;
1342 def : Pat<(riscv_setne (XLenVT GPR:$rs1)), (SLTU (XLenVT X0), GPR:$rs1)>;
1343 def : Pat<(XLenVT (setne (XLenVT GPR:$rs1), -1)), (SLTIU GPR:$rs1, -1)>;
1657 def : Pat<(riscv_sret_glue), (SRET (XLenVT X0), (XLenVT X0))>;
1658 def : Pat<(riscv_mret_glue), (MRET (XLenVT X0), (XLenVT X0))>;
1847 [(set GPR:$rd, (XLenVT (riscv_read_csr (XLenVT SR.Encoding))))]>,
1855 [(riscv_write_csr (XLenVT SR.Encoding), (XLenVT GPR:$val))]>,
1871 [(set GPR:$rd, (riscv_swap_csr (XLenVT SR.Encoding), (XLenVT GPR:$val)))]>,
1880 [(set GPR:$rd, (XLenVT (riscv_swap_csr (XLenVT SR.Encoding), uimm5:$val)))]>,
2059 (PseudoCCSUB (XLenVT GPR:$rs1), (XLenVT X0), /* COND_LT */ 2,
[all …]
H A DRISCVInstrInfoVVLPatterns.td240 SDTCisVT<4, XLenVT> // Rounding mode
250 SDTCisVT<4, XLenVT> // Rounding mode
256 SDTCisSameAs<0, 5>, SDTCisVT<6, XLenVT>]>;
346 SDTCisVT<5, XLenVT>
483 SDTCisVT<6, XLenVT>
1473 (XLenVT timm:$policy))>;
1496 (XLenVT timm:$policy))>;
1515 (XLenVT timm:$policy))>;
2941 SDTCisVT<6, XLenVT>
2946 SDTCisVT<5, XLenVT>
[all …]
H A DRISCVInstrInfoXSf.td42 def tsimm5 : Operand<XLenVT>, TImmLeaf<XLenVT, [{return isInt<5>(Imm);}]> {
442 (XLenVT op1_kind:$op1),
448 (XLenVT op1_kind:$op1),
466 (XLenVT op1_kind:$op1),
472 (XLenVT op1_kind:$op1),
488 (XLenVT op1_kind:$op1),
493 (XLenVT op1_kind:$op1),
502 XLenVT, XLenVT, type, vti.Log2SEW,
621 defm : VPatVC_X<"x", "X", vti, XLenVT, GPR>;
622 defm : VPatVC_X<"i", "I", vti, XLenVT, tsimm5>;
[all …]
H A DRISCVInstrInfoZicbo.td20 ImmLeaf<XLenVT, [{return isShiftedInt<7, 5>(Imm);}]> {
79 def : Pat<(prefetch (AddrRegImmLsb00000 (XLenVT GPR:$rs1), simm12_lsb00000:$imm12),
82 def : Pat<(prefetch (AddrRegImmLsb00000 (XLenVT GPR:$rs1), simm12_lsb00000:$imm12),
85 def : Pat<(prefetch (AddrRegImmLsb00000 (XLenVT GPR:$rs1), simm12_lsb00000:$imm12),
H A DRISCVISelLowering.cpp1351 XLenVT, LibCall); in RISCVTargetLowering()
5456 SDValue Res = DAG.getSetCC(DL, XLenVT, AND, DAG.getConstant(0, DL, XLenVT), in LowerIS_FPCLASS()
8778 XLenVT); in LowerINTRINSIC_W_CHAIN()
8926 XLenVT); in LowerINTRINSIC_VOID()
9500 DAG.getVScale(DL, XLenVT, APInt(XLenVT.getSizeInBits(), RemIdx)); in lowerINSERT_SUBVECTOR()
9638 DAG.getVScale(DL, XLenVT, APInt(XLenVT.getSizeInBits(), RemIdx)); in lowerEXTRACT_SUBVECTOR()
13927 if (VT == XLenVT) in performFP_TO_INTCombine()
13954 if (DstVT != XLenVT) in performFP_TO_INT_SATCombine()
15026 const MVT XLenVT = in legalizeScatterGatherIndexType() local
17486 LocVT = XLenVT; in CC_RISCV()
[all …]
H A DRISCVInstrInfoVSDPatterns.td25 (xor node:$in, (riscv_vmset_vl (XLenVT srcvalue)))>;
133 (vop_type (SplatPatKind (XLenVT xop_kind:$rs2))))),
585 (vti.Mask true_mask), (XLenVT srcvalue))),
594 (vti.Mask true_mask), (XLenVT srcvalue))),
603 (vti.Mask true_mask), (XLenVT srcvalue))),
620 (vti.Mask true_mask), (XLenVT srcvalue))),
633 (vti.Mask true_mask), (XLenVT srcvalue))),
889 (vti.Vector (SplatPat (XLenVT GPR:$rs2)))),
936 def : Pat<(sub (vti.Vector (SplatPat (XLenVT GPR:$rs2))),
1085 (vti.Mask true_mask), (XLenVT srcvalue))),
[all …]
H A DRISCVInstrInfoA.td110 def : StPat<atomic_store_8, SB, GPR, XLenVT>;
111 def : StPat<atomic_store_16, SH, GPR, XLenVT>;
112 def : StPat<atomic_store_32, SW, GPR, XLenVT>;
122 multiclass AMOPat<string AtomicOp, string BaseInst, ValueType vt = XLenVT,
227 def : Pat<(XLenVT (atomic_load_nand_32_monotonic GPR:$addr, GPR:$incr)),
229 def : Pat<(XLenVT (atomic_load_nand_32_acquire GPR:$addr, GPR:$incr)),
231 def : Pat<(XLenVT (atomic_load_nand_32_release GPR:$addr, GPR:$incr)),
233 def : Pat<(XLenVT (atomic_load_nand_32_acq_rel GPR:$addr, GPR:$incr)),
235 def : Pat<(XLenVT (atomic_load_nand_32_seq_cst GPR:$addr, GPR:$incr)),
323 ValueType vt = XLenVT> {
[all …]
H A DRISCVInstrInfoZk.td23 def SDT_RISCVZkByteSelect : SDTypeProfile<1, 3, [SDTCisVT<0, XLenVT>,
24 SDTCisVT<1, XLenVT>,
25 SDTCisVT<2, XLenVT>,
148 : Pat<(XLenVT (OpNode (XLenVT GPR:$rs1), (XLenVT GPR:$rs2), byteselect:$imm)),
H A DRISCVInstrInfoZvk.td18 def tuimm5 : Operand<XLenVT>, TImmLeaf<XLenVT, [{return isUInt<5>(Imm);}]> {
692 VLOpFrag, (XLenVT timm:$policy))),
696 GPR:$vl, sew, (XLenVT timm:$policy))>;
711 VLOpFrag, (XLenVT timm:$policy))),
715 GPR:$vl, sew, (XLenVT timm:$policy))>;
783 vti.Vector, vti.Vector, XLenVT, vti.Mask,
799 (XLenVT uimm6:$rs1),
813 (XLenVT uimm6:$rs1),
815 VLOpFrag, (XLenVT timm:$policy))),
842 Wti.Vector, Vti.Vector, XLenVT, Vti.Mask,
[all …]
H A DRISCVInstrInfoF.td26 : SDTypeProfile<1, 2, [SDTCisVT<0, XLenVT>, SDTCisFP<1>,
27 SDTCisVT<2, XLenVT>]>;
31 SDTCisVT<3, XLenVT>]>;
33 : SDTypeProfile<1, 1, [SDTCisVT<0, XLenVT>, SDTCisFP<1>]>;
129 def frmarg : Operand<XLenVT> {
149 def frmarglegacy : Operand<XLenVT> {
619 def : Pat<(XLenVT (strict_fsetccs FPR32:$rs1, FPR32:$rs2, SETEQ)),
622 def : Pat<(XLenVT (strict_fsetccs FPR32:$rs1, FPR32:$rs2, SETOEQ)),
626 def : Pat<(XLenVT (strict_fsetccs FPR32:$rs1, FPR32:$rs1, SETEQ)),
628 def : Pat<(XLenVT (strict_fsetccs FPR32:$rs1, FPR32:$rs1, SETOEQ)),
[all …]
H A DRISCVInstrInfoD.td412 def : Pat<(XLenVT (strict_fsetccs FPR64:$rs1, FPR64:$rs2, SETEQ)),
415 def : Pat<(XLenVT (strict_fsetccs FPR64:$rs1, FPR64:$rs2, SETOEQ)),
419 def : Pat<(XLenVT (strict_fsetccs FPR64:$rs1, FPR64:$rs1, SETEQ)),
421 def : Pat<(XLenVT (strict_fsetccs FPR64:$rs1, FPR64:$rs1, SETOEQ)),
432 def : Pat<(XLenVT (strict_fsetccs (f64 FPR64INX:$rs1), FPR64INX:$rs2, SETEQ)),
439 def : Pat<(XLenVT (strict_fsetccs (f64 FPR64INX:$rs1), FPR64INX:$rs1, SETEQ)),
452 def : Pat<(XLenVT (strict_fsetccs FPR64IN32X:$rs1, FPR64IN32X:$rs2, SETEQ)),
455 def : Pat<(XLenVT (strict_fsetccs FPR64IN32X:$rs1, FPR64IN32X:$rs2, SETOEQ)),
459 def : Pat<(XLenVT (strict_fsetccs FPR64IN32X:$rs1, FPR64IN32X:$rs1, SETEQ)),
461 def : Pat<(XLenVT (strict_fsetccs FPR64IN32X:$rs1, FPR64IN32X:$rs1, SETOEQ)),
[all …]
H A DRISCVISelDAGToDAG.cpp320 MVT XLenVT = Subtarget->getXLenVT(); in addVectorLoadStoreOperands() local
384 MVT XLenVT = Subtarget->getXLenVT(); in selectVLSEGFF() local
554 MVT XLenVT = Subtarget->getXLenVT(); in selectVSETVLI() local
586 VLOperand = CurDAG->getRegister(RISCV::X0, XLenVT); in selectVSETVLI()
831 MVT XLenVT = Subtarget->getXLenVT(); in Select() local
900 Imm = CurDAG->getRegister(RISCV::X0, XLenVT); in Select()
1433 if (Src2.getValueType() != XLenVT) in Select()
1466 Log2_32(Src1VT.getScalarSizeInBits()), DL, XLenVT); in Select()
1492 if (Src2.getValueType() != XLenVT) in Select()
1545 Log2_32(Src1VT.getScalarSizeInBits()), DL, XLenVT); in Select()
[all …]
H A DRISCVInstrInfoC.td21 def uimmlog2xlennonzero : RISCVOp, ImmLeaf<XLenVT, [{
64 ImmLeaf<XLenVT, [{return (Imm == 0);}]> {
82 ImmLeaf<XLenVT, [{return (Imm != 0) &&
100 ImmLeaf<XLenVT, [{return isShiftedUInt<5, 2>(Imm);}]> {
115 ImmLeaf<XLenVT, [{return isShiftedUInt<6, 2>(Imm);}]> {
130 ImmLeaf<XLenVT, [{return isShiftedUInt<5, 3>(Imm);}]> {
145 ImmLeaf<XLenVT, [{return isShiftedInt<8, 1>(Imm);}]> {
178 ImmLeaf<XLenVT,
194 ImmLeaf<XLenVT,
209 def simm12_lsb0 : Operand<XLenVT>,
[all …]
H A DRISCVInstrInfoVPseudos.td237 def VLOpFrag : PatFrag<(ops), (XLenVT (VLOp (XLenVT AVL:$vl)))>;
242 def VLMax : OutPatFrag<(ops), (XLenVT -1)>;
4004 (XLenVT timm:$round),
4012 (XLenVT timm:$round),
4051 (XLenVT timm:$round),
4060 (XLenVT timm:$round),
4158 (XLenVT timm:$round),
4164 (XLenVT timm:$round),
4180 (XLenVT timm:$round),
4186 (XLenVT timm:$round),
[all …]
H A DRISCVInstrInfoZfh.td19 : SDTypeProfile<1, 1, [SDTCisFP<0>, SDTCisVT<1, XLenVT>]>;
21 : SDTypeProfile<1, 1, [SDTCisVT<0, XLenVT>, SDTCisFP<1>]>;
368 def : Pat<(XLenVT (strict_fsetccs (f16 FPR16:$rs1), FPR16:$rs2, SETEQ)),
371 def : Pat<(XLenVT (strict_fsetccs (f16 FPR16:$rs1), FPR16:$rs2, SETOEQ)),
375 def : Pat<(XLenVT (strict_fsetccs (f16 FPR16:$rs1), (f16 FPR16:$rs1), SETEQ)),
383 def : Pat<(XLenVT (strict_fsetccs FPR16INX:$rs1, FPR16INX:$rs2, SETEQ)),
386 def : Pat<(XLenVT (strict_fsetccs FPR16INX:$rs1, FPR16INX:$rs2, SETOEQ)),
390 def : Pat<(XLenVT (strict_fsetccs FPR16INX:$rs1, FPR16INX:$rs1, SETEQ)),
392 def : Pat<(XLenVT (strict_fsetccs FPR16INX:$rs1, FPR16INX:$rs1, SETOEQ)),
425 def : Pat<(f16 (load (AddrRegImm (XLenVT GPR:$rs1), simm12:$imm12))),
[all …]
H A DRISCVInstrInfoZfa.td26 def loadfpimm : Operand<XLenVT> {
38 def rtzarg : Operand<XLenVT> {
H A DRISCVInstrInfoZa.td70 multiclass AMOCASPat<string AtomicOp, string BaseInst, ValueType vt = XLenVT,
H A DRISCVInstrInfoXCV.td662 def cv_tuimm2 : TImmLeaf<XLenVT, [{return isUInt<2>(Imm);}]>;
663 def cv_tuimm5 : TImmLeaf<XLenVT, [{return isUInt<5>(Imm);}]>;
664 def cv_uimm10 : ImmLeaf<XLenVT, [{return isUInt<10>(Imm);}]>;
705 def : Pat<(bitreverse (XLenVT GPR:$rs)), (CV_BITREV GPR:$rs, 0, 0)>;
H A DRISCVRegisterInfo.td119 def XLenVT : ValueTypeByHwMode<[RV32, RV64],
131 : RegisterClass<"RISCV", [XLenVT, XLenFVT, i32], 32, regList> {
462 def VCSR : RegisterClass<"RISCV", [XLenVT], 32,
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/RISCV/GISel/
H A DRISCVCallLowering.cpp473 const MVT XLenVT = Subtarget.getXLenVT(); in saveVarArgRegisters() local
478 CCValAssign::getReg(I + MF.getFunction().getNumOperands(), XLenVT, in saveVarArgRegisters()
479 ArgRegs[I], XLenVT, CCValAssign::Full)); in saveVarArgRegisters()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/CSKY/
H A DCSKYISelLowering.cpp369 const MVT XLenVT = MVT::i32; in LowerFormalArguments() local
404 SDValue ArgValue = DAG.getCopyFromReg(Chain, DL, Reg, XLenVT); in LowerFormalArguments()
518 MVT XLenVT = MVT::i32; in LowerCall() local
555 SDValue SizeNode = DAG.getConstant(Size, DL, XLenVT); in LowerCall()
1273 MVT XLenVT = MVT::i32; in LowerGlobalTLSAddress() local
1296 DAG.getConstant(Offset, DL, XLenVT)); in LowerGlobalTLSAddress()

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