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Searched refs:XD (Results 1 – 25 of 27) sorted by relevance

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/freebsd-14.2/contrib/ncurses/progs/
H A Dtparm_type.c50 #define XD(code, onlyname) TD(code, onlyname, onlyname, onlyname) in tparm_type() macro
63 XD(Str, "Cs"), in tparm_type()
64 XD(Str_Str, "Ms"), in tparm_type()
/freebsd-14.2/contrib/llvm-project/llvm/utils/TableGen/
H A DX86RecognizableInstr.cpp213 else if (OpPrefix == X86Local::XD) in insnContext()
227 else if (OpPrefix == X86Local::XD) in insnContext()
241 else if (OpPrefix == X86Local::XD) in insnContext()
253 else if (OpPrefix == X86Local::XD) in insnContext()
269 else if (OpPrefix == X86Local::XD) in insnContext()
284 } else if (OpPrefix == X86Local::XD) in insnContext()
301 else if (OpPrefix == X86Local::XD) in insnContext()
317 else if (HasVEX_L && OpPrefix == X86Local::XD) in insnContext()
327 else if (OpPrefix == X86Local::XD) in insnContext()
358 else if (OpPrefix == X86Local::XD) in insnContext()
[all …]
H A DX86RecognizableInstr.h171 enum { PD = 1, XS = 2, XD = 3, PS = 4 }; enumerator
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86InstrSNP.td26 TB, XD, Requires<[In64BitMode]>;
30 TB, XD, Requires<[Not64BitMode]>;
34 def RMPUPDATE: I<0x01, MRM_FE, (outs), (ins), "rmpupdate", []>, TB, XD,
H A DX86InstrAMX.td34 T8, XD;
58 VEX, T8, XD;
104 VEX, VVVV, T8, XD;
206 []>, VEX, VVVV, T8, XD;
H A DX86InstrRAOINT.td44 defm AOR : RAOINT_BASE<"or" >, T8, XD;
H A DX86InstrUtils.td40 class XD { Prefix OpPrefix = XD; }
75 class AVX512XDIi8Base : TB, XD {
486 !if(!eq(OpPrefix.Value, XD.Value), [UseSSE2],
503 !if(!eq(OpPrefix.Value, XD.Value), [UseSSE2],
598 // SDI - SSE2 instructions with XD prefix.
599 // SDIi8 - SSE2 instructions with ImmT == Imm8 and XD prefix.
604 // VSDI - SSE2 scalar instructions with XD prefix in AVX form.
636 : I<o, F, outs, ins, !strconcat("v", asm), pattern>, TB, XD,
664 // S3DI - SSE3 instructions with XD prefix.
672 : I<o, F, outs, ins, asm, pattern, SSEPackedDouble>, TB, XD,
[all …]
H A DX86InstrSSE.td1084 SSEPackedDouble>, TB, XD;
1087 SSEPackedDouble>, TB, XD, REX_W;
1099 TB, XD, VEX, VVVV, VEX_LIG;
1113 TB, XD;
1116 TB, XD, REX_W, SIMD_EXC;
1180 TB, XD, REX_W;
1345 TB, XD, Requires<[UseSSE2]>,
1868 TB, XD, VEX, VVVV, VEX_LIG, WIG;
8249 1>, T8, XD;
8261 1>, T8, XD;
[all …]
H A DX86InstrFormats.td144 def XD : Prefix<3>;
146 // that other instructions with this opcode use PD/XS/XD
H A DX86InstrMisc.td1391 defm PDEP32 : PdepPext<"pdep", Xi32, X86pdep>, XD, VEX;
1392 defm PDEP64 : PdepPext<"pdep", Xi64, X86pdep>, XD, REX_W, VEX;
1398 defm PDEP32 : PdepPext<"pdep", Xi32, X86pdep, "_EVEX">, XD, EVEX;
1399 defm PDEP64 : PdepPext<"pdep", Xi64, X86pdep, "_EVEX">, XD, REX_W, EVEX;
1486 TB, XD, Requires<[HasWAITPKG]>;
1548 T8, XD, AdSize16, Requires<[HasENQCMD, Not64BitMode]>;
1552 T8, XD, AdSize32, Requires<[HasENQCMD]>;
1556 T8, XD, AdSize64, Requires<[HasENQCMD, In64BitMode]>;
1629 [(int_x86_xsusldtrk)]>, TB, XD;
1631 [(int_x86_xresldtrk)]>, TB, XD;
H A DX86InstrShiftRotate.td543 "rorx", binop_ndd_args, []>, TA, XD, Sched<[WriteShift]> {
548 "rorx", binop_ndd_args, []>, TA, XD, Sched<[WriteShiftLd]> {
597 defm SHRX32: ShiftX<"shrx", Xi32>, XD;
598 defm SHRX64: ShiftX<"shrx", Xi64>, XD;
H A DX86InstrAVX512.td2670 VEX, TB, XD;
2674 VEX, TB, XD, REX_W;
2680 EVEX, TB, XD;
2684 EVEX, TB, XD, REX_W;
3418 TB, XD, EVEX_CD8<8, CD8VF>;
3424 TB, XD, REX_W, EVEX_CD8<16, CD8VF>;
7421 TB, XD, EVEX_CD8<64, CD8VT1>;
7602 "{l}">, TB, XD, EVEX_CD8<64, CD8VT1>;
7615 "{l}">, TB, XD, EVEX_CD8<64, CD8VT1>;
8695 SchedWriteCvtDQ2PS>, REX_W, TB, XD,
[all …]
H A DX86InstrSystem.td436 def RDMSRLIST : I<0x01, MRM_C6, (outs), (ins), "rdmsrlist", []>, TB, XD;
442 [(set GR64:$dst, (int_x86_urdmsr GR64:$src))]>, T8, XD;
445 [(set GR64:$dst, (int_x86_urdmsr i64immSExt32_su:$imm))]>, T_MAP7, XD, VEX;
H A DX86InstrArithmetic.td1371 (ins t.RegClass:$src), "mulx", mulx_args, []>, T8, XD, VEX,
1375 (ins t.MemOperand:$src), "mulx", mulx_args, []>, T8, XD, VEX,
1381 (ins t.RegClass:$src), "mulx", mulx_args, []>, T8, XD,
1386 (ins t.MemOperand:$src), "mulx", mulx_args, []>, T8, XD,
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/X86/MCTargetDesc/
H A DX86ATTInstPrinter.cpp105 else if ((Desc.TSFlags & X86II::OpPrefixMask) == X86II::XD) in printVecCompareInstr()
208 } else if ((Desc.TSFlags & X86II::OpPrefixMask) == X86II::XD) { in printVecCompareInstr()
H A DX86IntelInstPrinter.cpp88 else if ((Desc.TSFlags & X86II::OpPrefixMask) == X86II::XD) in printVecCompareInstr()
198 } else if ((Desc.TSFlags & X86II::OpPrefixMask) == X86II::XD) { in printVecCompareInstr()
H A DX86BaseInfo.h731 XD = 3 << OpPrefixShift, enumerator
H A DX86MCCodeEmitter.cpp1045 case X86II::XD: in emitVEXOpcodePrefix()
1448 case X86II::XD: // F2 in emitOpcodePrefix()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCScheduleP8.td176 (instregex "^XSCV(S|U)XD(D|S)P$"),
/freebsd-14.2/contrib/sendmail/contrib/
H A Dmail.local.linux61 M"4P*'I..-H8F-0FD/[`*@ZSBM)K6Y%=CNCH1KWSTJT`)2\6&XD]QL';BD?FK
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64SchedExynosM3.td563 def : InstRW<[M3WriteNEONI], (instregex "^FMOV(DX|XD)Highr")>;
H A DAArch64SchedTSV110.td518 def : InstRW<[TSV110Wr_2cyc_1FSU1], (instregex "^FMOV(DX|WS|XD|SW|DXHigh|XDHigh)r$")>;
H A DAArch64SchedFalkorDetails.td1149 def : InstRW<[FalkorWr_FMOV], (instregex "^FMOV(WS|XD|XDHigh)r$")>;
/freebsd-14.2/share/misc/
H A Dpci_vendors9788 1014 00ba MagicGraph 128XD
9789 1025 1007 MagicGraph 128XD
9790 1028 0074 MagicGraph 128XD
9791 1028 0075 MagicGraph 128XD
9792 1028 007d MagicGraph 128XD
9793 1028 007e MagicGraph 128XD
9794 1033 802f MagicGraph 128XD
9795 104d 801b MagicGraph 128XD
9796 104d 802f MagicGraph 128XD
9797 104d 830b MagicGraph 128XD
[all …]
H A Dusb_vendors7277 0041 XD-0405-U [Intuos2 (4x5)]
7278 0042 XD-0608-U [Intuos2 (6x8)]
7279 0043 XD-0912-U [Intuos2 (9x12)]
7280 0044 XD-1212-U [Intuos2 (12x12)]
7281 0045 XD-1218-U [Intuos2 (12x18)]
13065 0002 XD-2 [Spike]
18608 1336 SDHC/MicroSD/MMC/MS/M2/CF/XD Flash Card Reader
19201 1105 SM-MS/Pro-MMC-XD Card Reader

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