Searched refs:WidenVT (Results 1 – 6 of 6) sorted by relevance
| /freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | LegalizeVectorTypes.cpp | 4397 if (VT == WidenVT) in CollectOpsToWiden() 4452 if (VT == WidenVT) in CollectOpsToWiden() 4473 EVT VT = WidenVT; in WidenVecRes_BinaryCanTrap() 4563 EVT VT = WidenVT; in WidenVecRes_StrictFP() 5048 if (WidenVT.bitsEq(NInVT)) { in WidenVecRes_BITCAST() 5077 if (WidenVT.bitsEq(InVT)) in WidenVecRes_BITCAST() 5797 assert(InOp1.getValueType() == WidenVT && InOp2.getValueType() == WidenVT); in WidenVecRes_Select() 5823 assert(InOp1.getValueType() == WidenVT && InOp2.getValueType() == WidenVT); in WidenVecRes_Select() 5840 return DAG.getUNDEF(WidenVT); in WidenVecRes_UNDEF() 5919 return DAG.getVectorShuffle(WidenVT, dl, ReverseVal, DAG.getUNDEF(WidenVT), in WidenVecRes_VECTOR_REVERSE() [all …]
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| H A D | SelectionDAGBuilder.cpp | 718 EVT WidenVT = in getCopyToPartsVector() local 721 SDValue Widened = widenVectorToPartType(DAG, Val, DL, WidenVT); in getCopyToPartsVector()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.cpp | 4755 MVT WidenVT = MVT::getVectorVT(MVT::i8, VT.getVectorElementCount()); in lowerVECTOR_SHUFFLE() local 4756 V1 = DAG.getNode(ISD::ZERO_EXTEND, DL, WidenVT, V1); in lowerVECTOR_SHUFFLE() 4757 V2 = V2.isUndef() ? DAG.getUNDEF(WidenVT) in lowerVECTOR_SHUFFLE() 4758 : DAG.getNode(ISD::ZERO_EXTEND, DL, WidenVT, V2); in lowerVECTOR_SHUFFLE() 4759 SDValue Shuffled = DAG.getVectorShuffle(WidenVT, DL, V1, V2, SVN->getMask()); in lowerVECTOR_SHUFFLE() 4760 return DAG.getSetCC(DL, VT, Shuffled, DAG.getConstant(0, DL, WidenVT), in lowerVECTOR_SHUFFLE() 9888 MVT WidenVT = MVT::getVectorVT(MVT::i8, VecVT.getVectorElementCount()); in lowerVECTOR_REVERSE() local 9889 SDValue Op1 = DAG.getNode(ISD::ZERO_EXTEND, DL, WidenVT, Op.getOperand(0)); in lowerVECTOR_REVERSE() 9890 SDValue Op2 = DAG.getNode(ISD::VECTOR_REVERSE, DL, WidenVT, Op1); in lowerVECTOR_REVERSE()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 32209 MVT WidenVT = getTypeToTransformTo(*DAG.getContext(), VT).getSimpleVT(); in ReplaceNodeResults() local 32215 unsigned WidenNumElts = WidenVT.getVectorNumElements(); in ReplaceNodeResults() 32224 Res = widenSubVector(WidenVT, Res, false, Subtarget, DAG, dl); in ReplaceNodeResults() 32242 Results.push_back(DAG.getBuildVector(WidenVT, dl, Ops)); in ReplaceNodeResults() 32252 Results.push_back(DAG.getNode(X86ISD::VTRUNC, dl, WidenVT, In)); in ReplaceNodeResults() 32259 Results.push_back(DAG.getNode(X86ISD::VTRUNC, dl, WidenVT, In)); in ReplaceNodeResults() 32289 Results.push_back(DAG.getNode(ISD::TRUNCATE, dl, WidenVT, WidenIn)); in ReplaceNodeResults()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.cpp | 6583 MVT WidenVT = MVT::getVectorVT(MVT::getIntegerVT(EltSize), NumElts); in LowerCTPOP() local 6584 Res = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, WidenVT, Ops); in LowerCTPOP()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 9188 MVT WidenVT = MVT::getVectorVT(MVT::getIntegerVT(EltSize), NumElts); in LowerCTPOP_PARITY() local 9190 ISD::INTRINSIC_WO_CHAIN, DL, WidenVT, in LowerCTPOP_PARITY()
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