| /freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | LegalizeVectorTypes.cpp | 5499 unsigned NumElts = WideVT.getVectorNumElements(); in WidenVecRes_MGATHER() 5762 EVT WideVT = ((NarrowVT == VT0) ? VT1 : VT0); in WidenVSELECTMask() local 5764 MaskVT = WideVT; in WidenVSELECTMask() 6276 Res = DAG.getNode(Opcode, dl, WideVT, InOp); in WidenVecOp_Convert() 6602 EVT WideVT = StVal.getValueType(); in WidenVecOp_MSTORE() local 6613 EVT WideVT = EVT::getVectorVT(*DAG.getContext(), in WidenVecOp_MSTORE() local 6616 StVal = ModifyToType(StVal, WideVT); in WidenVecOp_MSTORE() 6791 EVT WideVT = Op.getValueType(); in WidenVecOp_VECREDUCE() local 6804 if (WideVT.isScalableVector()) { in WidenVecOp_VECREDUCE() 6829 EVT WideVT = Op.getValueType(); in WidenVecOp_VECREDUCE_SEQ() local [all …]
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| H A D | TargetLowering.cpp | 6274 WideVT = EVT::getVectorVT(*DAG.getContext(), WideVT, in BuildSDIV() 6279 Y = DAG.getNode(ISD::MUL, dl, WideVT, X, Y); in BuildSDIV() 6280 Y = DAG.getNode(ISD::SRL, dl, WideVT, Y, in BuildSDIV() 6460 WideVT = EVT::getVectorVT(*DAG.getContext(), WideVT, in BuildUDIV() 6466 Y = DAG.getNode(ISD::SRL, dl, WideVT, Y, in BuildUDIV() 10497 WideVT = in expandMULO() 10512 } else if (isTypeLegal(WideVT)) { in expandMULO() 10530 if (WideVT == MVT::i16) in expandMULO() 10532 else if (WideVT == MVT::i32) in expandMULO() 10534 else if (WideVT == MVT::i64) in expandMULO() [all …]
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| H A D | LegalizeIntegerTypes.cpp | 1103 EVT WideVT = EVT::getIntegerVT(*DAG.getContext(), VTSize * 2); in earlyExpandDIVFIX() local 1105 WideVT = EVT::getVectorVT(*DAG.getContext(), WideVT, in earlyExpandDIVFIX() 1107 LHS = DAG.getExtOrTrunc(Signed, LHS, dl, WideVT); in earlyExpandDIVFIX() 1108 RHS = DAG.getExtOrTrunc(Signed, RHS, dl, WideVT); in earlyExpandDIVFIX() 4819 EVT WideVT = in ExpandIntRes_XMULO() local 4821 SDValue LHS = DAG.getNode(ISD::SIGN_EXTEND, dl, WideVT, N->getOperand(0)); in ExpandIntRes_XMULO() 4822 SDValue RHS = DAG.getNode(ISD::SIGN_EXTEND, dl, WideVT, N->getOperand(1)); in ExpandIntRes_XMULO() 4823 SDValue Mul = DAG.getNode(ISD::MUL, dl, WideVT, LHS, RHS); in ExpandIntRes_XMULO()
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| H A D | DAGCombiner.cpp | 8922 EVT WideVT = EVT::getIntegerVT(Context, WideNumBits); in mergeTruncStores() local 8923 if (WideVT != MVT::i16 && WideVT != MVT::i32 && WideVT != MVT::i64) in mergeTruncStores() 8965 else if (SourceValue.getValueType() != WideVT) { in mergeTruncStores() 8966 if (WideVal.getValueType() == WideVT || in mergeTruncStores() 9035 if (WideVT != SourceValue.getValueType()) { in mergeTruncStores() 10219 EVT WideVT = LeftOp.getValueType(); in combineShiftToMULH() local 10221 assert((WideVT == RightOp.getValueType()) && in combineShiftToMULH() 10226 if (WideVT.getScalarSizeInBits() != 2 * NarrowVTSize) in combineShiftToMULH() 12242 EVT WideSetCCVT = getSetCCResultType(WideVT); in visitVSELECT() 24267 EVT WideVT = N0.getValueType(); in foldExtractSubvectorFromShuffleVector() local [all …]
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| H A D | SelectionDAG.cpp | 12362 EVT WideVT = EVT::getVectorVT(*getContext(), VT.getVectorElementType(), in WidenVector() local 12364 return getNode(ISD::INSERT_SUBVECTOR, DL, WideVT, getUNDEF(WideVT), N, in WidenVector()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/SystemZ/ |
| H A D | SystemZISelLowering.cpp | 4561 EVT WideVT = MVT::i32; in getCSAddressAndShifts() local 4571 BitShift = DAG.getNode(ISD::TRUNCATE, DL, WideVT, BitShift); in getCSAddressAndShifts() 4575 NegBitShift = DAG.getNode(ISD::SUB, DL, WideVT, in getCSAddressAndShifts() 4589 EVT WideVT = MVT::i32; in lowerATOMIC_LOAD_OP() local 4590 if (NarrowVT == WideVT) in lowerATOMIC_LOAD_OP() 4616 Src2 = DAG.getNode(ISD::SHL, DL, WideVT, Src2, in lowerATOMIC_LOAD_OP() 4620 Src2 = DAG.getNode(ISD::OR, DL, WideVT, Src2, in lowerATOMIC_LOAD_OP() 4624 SDVTList VTList = DAG.getVTList(WideVT, MVT::Other); in lowerATOMIC_LOAD_OP() 4626 DAG.getConstant(BitSize, DL, WideVT) }; in lowerATOMIC_LOAD_OP() 4684 EVT WideVT = NarrowVT == MVT::i64 ? MVT::i64 : MVT::i32; in lowerATOMIC_CMP_SWAP() local [all …]
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 12315 if (!WideVT.is256BitVector()) in lowerShuffleOfExtractsAsVperm() 12340 SDValue Shuf = DAG.getVectorShuffle(WideVT, DL, WideVec, DAG.getUNDEF(WideVT), in lowerShuffleOfExtractsAsVperm() 20066 MVT WideVT = ExtVT; in LowerZERO_EXTEND_Mask() local 20088 if (WideVT != VT) in LowerZERO_EXTEND_Mask() 20817 IsStrict ? DAG.getConstantFP(0.0, dl, WideVT) : DAG.getUNDEF(WideVT); in LowerFP_TO_INT() 20847 IsStrict ? DAG.getConstantFP(0.0, dl, WideVT) : DAG.getUNDEF(WideVT); in LowerFP_TO_INT() 24164 MVT WideVT = ExtVT; in LowerSIGN_EXTEND_Mask() local 24191 if (WideVT != VT) in LowerSIGN_EXTEND_Mask() 28216 if (TLI.isTypeLegal(WideVT)) { in LowerABD() 29979 MVT WideVT = in LowerRotate() local [all …]
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.cpp | 4503 MVT WideVT = in getWideningInterleave() local 4506 MVT WideContainerVT = WideVT; // <vscale x n x ty*2> in getWideningInterleave() 6007 MVT WideVT = VT.changeVectorElementType(MVT::i8); in LowerOperation() local 7918 Vec = DAG.getNode(ISD::ZERO_EXTEND, DL, WideVT, Vec); in lowerINSERT_VECTOR_ELT() 8128 MVT WideVT = MVT::getVectorVT(WideEltVT, WidenVecLen); in lowerEXTRACT_VECTOR_ELT() local 8129 Vec = DAG.getNode(ISD::BITCAST, DL, WideVT, Vec); in lowerEXTRACT_VECTOR_ELT() 8142 Vec = DAG.getNode(ISD::ZERO_EXTEND, DL, WideVT, Vec); in lowerEXTRACT_VECTOR_ELT() 9660 MVT WideVT = VT.changeVectorElementType(MVT::i8); in widenVectorOpsToi8() local 9677 DAG.getConstant(0, DL, WideVT), ISD::SETNE)); in widenVectorOpsToi8() 15624 EVT WideVT = EVT::getVectorVT(*DAG.getContext(), WideScalarVT, in PerformDAGCombine() local [all …]
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCISelLowering.cpp | 7996 EVT WideVT = EVT::getVectorVT(*DAG.getContext(), EltVT, WideNumElts); in LowerTRUNCATEVector() local 8012 Op2 = DAG.getUNDEF(WideVT); in LowerTRUNCATEVector() 8030 Op1 = DAG.getNode(ISD::BITCAST, DL, WideVT, Op1); in LowerTRUNCATEVector() 8031 Op2 = DAG.getNode(ISD::BITCAST, DL, WideVT, Op2); in LowerTRUNCATEVector() 8032 return DAG.getVectorShuffle(WideVT, DL, Op1, Op2, ShuffV); in LowerTRUNCATEVector() 8572 EVT WideVT = EVT::getVectorVT(*DAG.getContext(), EltVT, WideNumElts); in widenVec() local 8581 return DAG.getNode(ISD::CONCAT_VECTORS, dl, WideVT, Ops); in widenVec() 8603 EVT WideVT = Wide.getValueType(); in LowerINT_TO_FPVector() local 8604 unsigned WideNumElts = WideVT.getVectorNumElements(); in LowerINT_TO_FPVector() 8621 SignedConv ? DAG.getUNDEF(WideVT) : DAG.getConstant(0, dl, WideVT); in LowerINT_TO_FPVector() [all …]
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelDAGToDAG.cpp | 2155 EVT WideVT = RegSeq.getOperand(1)->getValueType(0); in SelectLoadLane() local 2159 SDValue NV = CurDAG->getTargetExtractSubreg(QSubs[i], dl, WideVT, SuperReg); in SelectLoadLane() 2206 EVT WideVT = RegSeq.getOperand(1)->getValueType(0); in SelectPostLoadLane() local 2210 SDValue NV = CurDAG->getTargetExtractSubreg(QSubs[i], dl, WideVT, in SelectPostLoadLane()
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| H A D | AArch64ISelLowering.cpp | 13622 EVT WideVT = getPackedSVEVectorVT(InVT.getVectorElementCount()); in LowerINSERT_SUBVECTOR() local 13627 Vec1 = getSVESafeBitCast(WideVT, Vec1, DAG); in LowerINSERT_SUBVECTOR() 13630 Vec1 = DAG.getNode(ISD::ANY_EXTEND, DL, WideVT, Vec1); in LowerINSERT_SUBVECTOR() 13638 SDValue HiVec0 = DAG.getNode(AArch64ISD::UUNPKHI, DL, WideVT, Vec0); in LowerINSERT_SUBVECTOR() 13643 SDValue LoVec0 = DAG.getNode(AArch64ISD::UUNPKLO, DL, WideVT, Vec0); in LowerINSERT_SUBVECTOR() 25961 EVT WideVT = VT.widenIntegerVectorElementType(*DAG.getContext()); in LowerFixedLengthVectorIntDivideToSVE() local 25962 if (DAG.getTargetLoweringInfo().isTypeLegal(WideVT)) { in LowerFixedLengthVectorIntDivideToSVE() 25963 SDValue Op0 = DAG.getNode(ExtendOpcode, dl, WideVT, Op.getOperand(0)); in LowerFixedLengthVectorIntDivideToSVE() 25964 SDValue Op1 = DAG.getNode(ExtendOpcode, dl, WideVT, Op.getOperand(1)); in LowerFixedLengthVectorIntDivideToSVE() 25965 SDValue Div = DAG.getNode(Op.getOpcode(), dl, WideVT, Op0, Op1); in LowerFixedLengthVectorIntDivideToSVE()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/M68k/ |
| H A D | M68kISelLowering.cpp | 2033 EVT WideVT = WideVal.getValueType(); in EmitTest() local 2060 if (TLI.isOperationLegal(WideVal.getOpcode(), WideVT)) { in EmitTest()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Sparc/ |
| H A D | SparcISelLowering.cpp | 3175 EVT WideVT = MVT::i128; in LowerUMULO_SMULO() local 3199 RTLIB::MUL_I128, WideVT, in LowerUMULO_SMULO()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUISelLowering.cpp | 1806 EVT WideVT = in WidenOrSplitVectorLoad() local 1811 Load->getExtensionType(), SL, WideVT, Load->getChain(), BasePtr, SrcValue, in WidenOrSplitVectorLoad()
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