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Searched refs:WideReg (Results 1 – 4 of 4) sorted by relevance

/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/
H A DAArch64PreLegalizerCombiner.cpp90 Register WideReg; in matchICmpRedundantTrunc() local
92 if (!mi_match(LHS, MRI, m_GTrunc(m_Reg(WideReg))) || in matchICmpRedundantTrunc()
96 LLT WideTy = MRI.getType(WideReg); in matchICmpRedundantTrunc()
97 if (KB->computeNumSignBits(WideReg) <= in matchICmpRedundantTrunc()
101 MatchInfo = WideReg; in matchICmpRedundantTrunc()
107 GISelChangeObserver &Observer, Register &WideReg) { in applyICmpRedundantTrunc() argument
110 LLT WideTy = MRI.getType(WideReg); in applyICmpRedundantTrunc()
116 MI.getOperand(2).setReg(WideReg); in applyICmpRedundantTrunc()
659 Register WideReg; in tryToSimplifyUADDO() local
660 if (mi_match(U.getParent(), MRI, m_GZExt(m_Reg(WideReg)))) { in tryToSimplifyUADDO()
H A DAArch64CallLowering.cpp681 Register WideReg = MRI.createGenericVirtualRegister(LLT::scalar(8)); in lowerFormalArguments() local
682 OrigArg.Regs[0] = WideReg; in lowerFormalArguments()
683 BoolArgs.push_back({OrigReg, WideReg}); in lowerFormalArguments()
711 Register WideReg = KV.second; in lowerFormalArguments() local
712 LLT WideTy = MRI.getType(WideReg); in lowerFormalArguments()
716 OrigReg, MIRBuilder.buildAssertZExt(WideTy, WideReg, 1).getReg(0)); in lowerFormalArguments()
H A DAArch64InstructionSelector.cpp6075 Register WideReg = Vec.getReg(0); in selectVectorLoadLaneIntrinsic() local
6079 !emitNarrowVector(I.getOperand(Idx).getReg(), WideReg, MIB, MRI)) in selectVectorLoadLaneIntrinsic()
/freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/
H A DLoadStoreOpt.cpp381 Register WideReg; in doSingleStoreMerge() local
401 WideReg = Builder.buildConstant(WideValueTy, WideConst).getReg(0); in doSingleStoreMerge()
403 Builder.buildStore(WideReg, FirstStore->getPointerReg(), *WideMMO); in doSingleStoreMerge()