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Searched refs:WaveSize (Results 1 – 4 of 4) sorted by relevance

/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUSubtarget.cpp328 const unsigned WaveSize = getWavefrontSize(); in getMaxLocalMemSizeWithWaveCount() local
331 std::max(1u, (WorkGroupSize + WaveSize - 1) / WaveSize); in getMaxLocalMemSizeWithWaveCount()
352 const unsigned WaveSize = getWavefrontSize(); in getOccupancyWithLocalMemSize() local
367 const unsigned MaxGroupNumWaves = divideCeil(MaxWorkGroupSize, WaveSize); in getOccupancyWithLocalMemSize()
H A DSIMachineFunctionInfo.cpp406 unsigned WaveSize = ST.getWavefrontSize(); in allocateSGPRSpillToVGPRLane() local
411 if (NumLanes > WaveSize) in allocateSGPRSpillToVGPRLane()
422 unsigned LaneIndex = (NumSpillLanes % WaveSize); in allocateSGPRSpillToVGPRLane()
H A DAMDGPURegisterBankInfo.cpp1201 auto WaveSize = B.buildConstant(LLT::scalar(32), ST.getWavefrontSizeLog2()); in applyMappingDynStackAlloc() local
1202 auto ScaledSize = B.buildShl(IntPtrTy, AllocSize, WaveSize); in applyMappingDynStackAlloc()
4949 unsigned WaveSize = getSizeInBits(MI.getOperand(1).getReg(), MRI, *TRI); in getInstrMapping() local
4951 OpdsMapping[1] = AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, WaveSize); in getInstrMapping()
4952 OpdsMapping[3] = AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, WaveSize); in getInstrMapping()
H A DSIISelLowering.cpp4914 unsigned WaveSize = TRI->getRegSizeInBits(*Src2RC); in EmitInstrWithCustomInserter() local
4915 assert(WaveSize == 64 || WaveSize == 32); in EmitInstrWithCustomInserter()
4917 if (WaveSize == 64) { in EmitInstrWithCustomInserter()
4948 (WaveSize == 64) ? AMDGPU::S_CSELECT_B64 : AMDGPU::S_CSELECT_B32; in EmitInstrWithCustomInserter()
15920 unsigned WaveSize) { in hasCFUser() argument
15925 if (!IT || IT->getBitWidth() != WaveSize) in hasCFUser()
15959 Result = hasCFUser(U, Visited, WaveSize); in hasCFUser()