| /freebsd-14.2/sys/contrib/device-tree/Bindings/watchdog/ |
| H A D | gpio-wdt.txt | 5 - gpios: From common gpio binding; gpio connection to WDT reset pin.
9 the WDT counter. The watchdog timer is disabled when GPIO is
11 - level: Low or high level starts counting WDT timeout,
12 the opposite level disables the WDT. Active level is determined
|
| H A D | arm,sp805.txt | 3 SP805 WDT is a ARM Primecell Peripheral and has a standard-id register that
7 As SP805 WDT is a primecell IP, it follows the base bindings specified in
21 - interrupts: Should specify WDT interrupt number
22 - timeout-sec: Should specify default WDT timeout in seconds. If unset, the
|
| H A D | lpc18xx-wdt.txt | 1 * NXP LPC18xx Watchdog Timer (WDT)
5 - reg: Should contain WDT registers location and length
9 - interrupts: Should contain WDT interrupt
|
| H A D | imgpdc-wdt.txt | 1 *ImgTec PowerDown Controller (PDC) Watchdog Timer (WDT)
5 - reg : Should contain WDT registers location and length
9 - interrupts : Should contain WDT interrupt
|
| H A D | gpio-wdt.yaml | 18 description: GPIO connected to the WDT reset pin
25 Either a high-to-low or a low-to-high transition clears the WDT counter.
30 Low or high level starts counting WDT timeout, the opposite level
31 disables the WDT.
|
| H A D | xlnx,xps-timebase-wdt.yaml | 14 The Timebase watchdog timer(WDT) is a free-running 32 bit counter.
15 WDT uses a dual-expiration architecture. After one expiration of
16 the timeout interval, an interrupt is generated and the WDT state
19 expiration of the timeout interval, a WDT reset is generated.
|
| H A D | linux,wdt-gpio.yaml | 18 description: gpio connection to WDT reset pin
25 Either a high-to-low or a low-to-high transition clears the WDT counter.
30 Low or high level starts counting WDT timeout, the opposite level
31 disables the WDT.
|
| H A D | sirfsoc_wdt.txt | 1 SiRFSoC Timer and Watchdog Timer(WDT) Controller
5 - reg: Address range of tick timer/WDT register set
|
| H A D | omap-wdt.txt | 1 TI Watchdog Timer (WDT) Controller for OMAP
5 - ti,hwmods : Name of the hwmod associated to the WDT
|
| H A D | davinci-wdt.txt | 1 Texas Instruments DaVinci/Keystone Watchdog Timer (WDT) Controller
5 - reg : Should contain WDT registers location and length
|
| H A D | realtek,otto-wdt.yaml | 17 - Phase 1: During this phase, the WDT can be pinged to reset the timeout.
20 During this phase, pinging the WDT has no effect, and a reset is
21 unavoidable, unless the WDT is disabled.
|
| H A D | qca-ar7130-wdt.txt | 1 * Qualcomm Atheros AR7130 Watchdog Timer (WDT) Controller
|
| H A D | microchip,pic32-wdt.txt | 4 WDT is not cleared periodically in software.
|
| H A D | fsl-imx7ulp-wdt.yaml | 7 title: Freescale i.MX7ULP Watchdog Timer (WDT) Controller
|
| H A D | mpc8xxx-wdt.txt | 22 WDT: watchdog@0 {
|
| H A D | ti,rti-wdt.yaml | 48 * RTI WDT in main domain on J721e SoC. Assigned clocks are used to
|
| H A D | atmel-sama5d4-wdt.txt | 1 * Atmel SAMA5D4 Watchdog Timer (WDT) Controller
|
| H A D | atmel,sama5d4-wdt.yaml | 7 title: Atmel SAMA5D4 Watchdog Timer (WDT) Controller
|
| /freebsd-14.2/sys/contrib/device-tree/Bindings/power/reset/ |
| H A D | keystone-reset.txt | 29 - ti,wdt-list: WDT list that can cause SoC reset. It's not related
30 to WDT driver, it's just needed to enable a SoC related
|
| /freebsd-14.2/sys/contrib/device-tree/include/dt-bindings/clock/ |
| H A D | xlnx-zynqmp-clk.h | 87 #define WDT 75 macro
|
| H A D | xlnx-versal-clk.h | 47 #define WDT 38 macro
|
| /freebsd-14.2/sys/contrib/device-tree/Bindings/soc/renesas/ |
| H A D | renesas,r9a09g011-sys.yaml | 22 - WDT stop control
|
| H A D | renesas,rzg2l-sysc.yaml | 18 - WDT stop control
|
| /freebsd-14.2/sys/contrib/device-tree/Bindings/power/ |
| H A D | renesas,rzg2l-sysc.yaml | 18 - WDT stop control
|
| /freebsd-14.2/sys/contrib/device-tree/Bindings/mfd/ |
| H A D | samsung,exynos5433-lpass.txt | 18 UART, SLIMBUS, PCM, I2S, DMAC, Timers 0...4, VIC, WDT 0...1 devices.
|