| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMInstrNEON.td | 2511 (ins DPR:$Vm), IIC_VUNAD, OpcodeStr, Dt,"$Vd, $Vm", "",
2517 (ins QPR:$Vm), IIC_VUNAQ, OpcodeStr, Dt,"$Vd, $Vm", "",
2526 (ins DPR:$Vm), itin, OpcodeStr, Dt, "$Vd, $Vm", "",
2533 (ins QPR:$Vm), itin, OpcodeStr, Dt, "$Vd, $Vm", "",
2576 (ins QPR:$Vm), itin, OpcodeStr, Dt, "$Vd, $Vm", "",
2585 (ins QPR:$Vm), itin, OpcodeStr, Dt, "$Vd, $Vm", "",
2594 (ins DPR:$Vm), itin, OpcodeStr, Dt, "$Vd, $Vm", "",
2603 (ins DPR:$Vm), itin, OpcodeStr, Dt, "$Vd, $Vm", "",
3173 (ins DPR:$Vm), IIC_VSHLiD, OpcodeStr, Dt, "$Vd, $Vm", "",
3180 (ins QPR:$Vm), IIC_VSHLiD, OpcodeStr, Dt, "$Vd, $Vm", "",
[all …]
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| H A D | ARMInstrCDE.td | 375 bits<5> Vm;
379 let Inst{3-0} = Vm{4-1};
380 let Inst{5} = Vm{0};
388 bits<5> Vm;
392 let Inst{3-0} = Vm{3-0};
393 let Inst{5} = Vm{4};
443 bits<5> Vm;
450 let Inst{5} = Vm{0};
451 let Inst{3-0} = Vm{4-1};
459 bits<5> Vm;
[all …]
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| H A D | ARMInstrFormats.td | 2332 bits<5> Vm;
2347 bits<5> Vm;
2385 bits<5> Vm;
2407 bits<5> Vm;
2440 bits<5> Vm;
2457 bits<5> Vm;
2485 bits<5> Vm;
2506 bits<5> Vm;
2534 bits<5> Vm;
2605 bits<5> Vm;
[all …]
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64InstrInfo.td | 6054 (UZP1v16i8 V128:$Vn, V128:$Vm)>;
6057 (UZP1v8i16 V128:$Vn, V128:$Vm)>;
6060 (UZP1v4i32 V128:$Vn, V128:$Vm)>;
6065 (UZP1v16i8 V128:$Vn, V128:$Vm)>;
6857 // vaddv_[su]32 is special; -> ADDP Vd.2S,Vn.2S,Vm.2S; return Vd.s[0];Vn==Vm
6862 // vaddv_[su]32 is special; -> ADDP Vd.2S,Vn.2S,Vm.2S; return Vd.s[0];Vn==Vm
9151 // vaddv_[su]32 is special; -> ADDP Vd.2S,Vn.2S,Vm.2S; return Vd.s[0];Vn==Vm
9155 OutPatFrag<(ops node:$Vm, node:$Vn),
9159 (v8i8 node:$Vm),
9166 (odot_v8i8<DOT> V64:$Vm, V64:$Vn)>,
[all …]
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| H A D | AArch64InstrFormats.td | 8102 bits<5> Vm;
8106 let Inst{20-16} = Vm;
8123 bits<5> Vm;
8127 let Inst{20-16} = Vm;
11659 bits<5> Vm;
11661 let Inst{20-16} = Vm;
11669 "{\t$Vd.2d, $Vn.2d, $Vm.2d|.2d\t$Vd, $Vn, $Vm}", "">;
11675 "{\t$Vd.4s, $Vn.4s, $Vm.4s|.4s\t$Vd, $Vn, $Vm}", "">;
11686 bits<5> Vm;
11708 bits<5> Vm;
[all …]
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| H A D | AArch64InstrGISel.td | 462 // vaddv_[su]32 is special; -> ADDP Vd.2S,Vn.2S,Vm.2S; return Vd.s[0];Vn==Vm
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| H A D | SVEInstrFormats.td | 1694 : I<(outs zprty:$Zdn), (ins zprty:$_Zdn, srcOpType:$Vm),
1695 asm, "\t$Zdn, $Vm",
1698 bits<5> Vm;
1703 let Inst{9-5} = Vm;
1717 def : Pat<(nxv8f16 (op nxv8f16:$Zn, f16:$Vm)),
1719 def : Pat<(nxv4f32 (op nxv4f32:$Zn, f32:$Vm)),
1721 def : Pat<(nxv2f64 (op nxv2f64:$Zn, f64:$Vm)),
1724 def : Pat<(nxv8bf16 (op nxv8bf16:$Zn, bf16:$Vm)),
1729 (!cast<Instruction>(NAME # _B) $Zn, ZPR:$Vm)>;
1731 (!cast<Instruction>(NAME # _H) $Zn, ZPR:$Vm)>;
[all …]
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| /freebsd-14.2/secure/caroot/trusted/ |
| H A D | HiPKI_Root_CA_-_G1.pem | 119 /W3c1pzAtH2lsN0/Vm+h+fbkEkj9Bn8SV7apI09bA8PgcSojt/ewsTu8mL3WmKgM
|
| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/ARM/Disassembler/ |
| H A D | ARMDisassembler.cpp | 6017 unsigned Vm = (fieldFromInstruction(Insn, 0, 4) << 0); in DecodeVCVTD() local
6018 Vm |= (fieldFromInstruction(Insn, 5, 1) << 4); in DecodeVCVTD()
6061 if (!Check(S, DecodeDPRRegisterClass(Inst, Vm, Address, Decoder))) in DecodeVCVTD()
6076 unsigned Vm = (fieldFromInstruction(Insn, 0, 4) << 0); in DecodeVCVTQ() local
6077 Vm |= (fieldFromInstruction(Insn, 5, 1) << 4); in DecodeVCVTQ()
6120 if (!Check(S, DecodeQPRRegisterClass(Inst, Vm, Address, Decoder))) in DecodeVCVTQ()
6135 unsigned Vm = (fieldFromInstruction(Insn, 0, 4) << 0); in DecodeNEONComplexLane64Instruction() local
6136 Vm |= (fieldFromInstruction(Insn, 5, 1) << 4); in DecodeNEONComplexLane64Instruction()
6150 if (!Check(S, DecodeDPRRegisterClass(Inst, Vm, Address, Decoder))) in DecodeNEONComplexLane64Instruction()
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