Searched refs:VectorList (Results 1 – 5 of 5) sorted by relevance
| /freebsd-14.2/contrib/llvm-project/clang/utils/TableGen/ |
| H A D | ClangOpenCLBuiltinEmitter.cpp | 267 std::vector<int64_t> &VectorList) const;
887 std::vector<int64_t> VectorList = in EmitQualTypeFinder() local
889 OS << " QT.reserve(" << VectorList.size() * BaseTypes.size() << ");\n" in EmitQualTypeFinder()
890 << " for (unsigned I = 0; I < " << VectorList.size() << "; I++) {\n" in EmitQualTypeFinder()
1042 std::vector<int64_t> &VectorList) const { in getTypeLists()
1046 VectorList = in getTypeLists()
1063 getTypeLists(PossibleGenType, Flags, TypeList, VectorList); in getTypeLists()
1070 VectorList.push_back(Type->getValueAsInt("VecWidth")); in getTypeLists()
1083 std::vector<int64_t> VectorList; in expandTypesInSignature() local
1086 getTypeLists(Arg, Flags, TypeList, VectorList); in expandTypesInSignature()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/ARM/AsmParser/ |
| H A D | ARMAsmParser.cpp | 2122 return VectorList.Count == 1 && VectorList.LaneIndex <= 7; in isVecListOneDByteIndexed()
2127 return VectorList.Count == 1 && VectorList.LaneIndex <= 3; in isVecListOneDHWordIndexed()
2132 return VectorList.Count == 1 && VectorList.LaneIndex <= 1; in isVecListOneDWordIndexed()
2137 return VectorList.Count == 2 && VectorList.LaneIndex <= 7; in isVecListTwoDByteIndexed()
2142 return VectorList.Count == 2 && VectorList.LaneIndex <= 3; in isVecListTwoDHWordIndexed()
2147 return VectorList.Count == 2 && VectorList.LaneIndex <= 1; in isVecListTwoQWordIndexed()
2152 return VectorList.Count == 2 && VectorList.LaneIndex <= 3; in isVecListTwoQHWordIndexed()
2157 return VectorList.Count == 2 && VectorList.LaneIndex <= 1; in isVecListTwoDWordIndexed()
2162 return VectorList.Count == 3 && VectorList.LaneIndex <= 7; in isVecListThreeDByteIndexed()
2167 return VectorList.Count == 3 && VectorList.LaneIndex <= 3; in isVecListThreeDHWordIndexed()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AArch64/AsmParser/ |
| H A D | AArch64AsmParser.cpp | 498 struct VectorListOp VectorList; member
558 VectorList = o.VectorList; in AArch64Operand()
689 return VectorList.RegNum; in getVectorListStart()
694 return VectorList.Count; in getVectorListCount()
699 return VectorList.Stride; in getVectorListStride()
1404 VectorList.NumElements == 0 && in isImplicitlyTypedVectorList()
1413 if (VectorList.Count != NumRegs) in isTypedVectorList()
1419 if (VectorList.Stride != Stride) in isTypedVectorList()
2273 Op->VectorList.RegNum = RegNum; in CreateVectorList()
2274 Op->VectorList.Count = Count; in CreateVectorList()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64RegisterInfo.td | 566 multiclass VectorList<int count, RegisterClass Reg64, RegisterClass Reg128> {
667 defm VecListOne : VectorList<1, FPR64, FPR128>;
668 defm VecListTwo : VectorList<2, DD, QQ>;
669 defm VecListThree : VectorList<3, DDD, QQQ>;
670 defm VecListFour : VectorList<4, DDDD, QQQQ>;
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| /freebsd-14.2/contrib/llvm-project/clang/lib/Sema/ |
| H A D | OpenCLBuiltins.td | 272 // For example, if TypeList = <int, float> and VectorList = <1, 2, 4>, then it
298 IntList VectorList = _VectorList;
299 // The VecWidth field is ignored for GenericTypes. Use VectorList instead.
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